# US 9,438,261 B2 · Capacitance-to-digital converter and method for providing a digital output signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,261 B2 - Document ID: US9438261B2 - Status: Granted - Kind: B2 - Application number: 14/683,119 - Filed: 2015-04-09 - Published: 2015-10-15 - Granted: 2016-09-06 - Earliest claimed: 2014-04-09 - Assignees: Ams AG - Applicants: ams AG - Inventors: Jose Manuel Garcia Gonzalez; Joel Bertomeu Mestre; Rafael Serrano Gotarredona - Web page: https://patentgrep.com/patent/US9438261B2 ## CPC - H03M 1/1019: {by storing a corrected or correction value in a digital look-up table} - H03M 3/356: {Offset or drift compensation (removal of offset already present on the analogue input signal H03M3/494)} - H03M 3/382: {at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error} - G01R 27/2605: {Measuring capacitance (capacitive sensors G01D5/24)} - H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) - H03M 3/34: {by chopping} - H03M 3/458: {Analogue/digital converters using delta-sigma modulation as an intermediate step} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A capacitance-to-digital converter (10) comprises a capacitor arrangement (30), a converter (1) that is coupled on its input side to the capacitor arrangement (30) and a calibration unit (13) that is coupled on its input side to the converter (1). The capacitor arrangement (30) comprises an input capacitor (16). ## Claims ### Claim 1 A capacitance-to-digital converter, comprising: a capacitor arrangement comprising an input capacitor; a converter that is coupled on its input side to the capacitor arrangement; and a calibration unit that is coupled on its input side to the converter, wherein the converter comprises an interface circuit that is coupled on its input side to the capacitor arrangement and comprises a first integrator having a first amplifier as well as a first and a second integrating capacitor, wherein the interface circuit comprises a first and a second chopping unit, such that the first chopping unit couples a first and a second input of the first amplifier to a first terminal of the first integrating capacitor, and the second chopping unit couples the first and the second input of the first amplifier to a first terminal of the second integrating capacitor. ### Claim 2 (depends on 1) The capacitance-to-digital converter according to claim 1, wherein the calibration unit is configured to provide a digital output signal that has a polynomial dependency from an input signal of the calibration unit or a signal derived from the input signal. ### Claim 3 (depends on 1) The capacitance-to-digital converter according to claim 1, comprising a temperature sensor having an output coupled to the calibration unit and generating a temperature signal, wherein the calibration unit is configured to provide a digital output signal that has a polynomial dependency from an input signal of the calibration unit and from the temperature signal or a signal derived from the temperature signal. ### Claim 4 (depends on 1, 2) The capacitance-to-digital converter according to claim 1 or 2, comprising a memory that is coupled to the calibration unit, is realized as a non-volatile memory and stores calibration coefficients. ### Claim 5 (depends on 1, 2) The capacitance-to-digital converter according to claim 1 or 2, wherein the input capacitor is implemented as a capacitive sensor and the capacitor arrangement comprises a further capacitive sensor that detect the same parameter to be measured. ### Claim 6 (depends on 1, 2) The capacitance-to-digital converter according to claim 1 or 2, wherein the capacitor arrangement comprises a reference capacitor and the reference capacitor is realized such that the capacitance value of the reference capacitor can be trimmed or programmed. ### Claim 7 (depends on 1) The capacitance-to-digital converter according to claim 1, wherein the interface circuit comprises a chopping unit that is arranged between the capacitor arrangement and the first integrator. ### Claim 8 (depends on 1) The capacitance-to-digital converter according to claim 1, wherein a second terminal of the first integrating capacitor is coupled to a first output of the first amplifier, and a second terminal of the second integrating capacitor is coupled to a second output of the first amplifier. ### Claim 9 (depends on 1) The capacitance-to-digital converter according to claim 1, wherein the interface circuit comprises an input-common-mode feedback circuit that comprises a control terminal for receiving a control signal and is designed to be enabled or disabled by the control signal. ### Claim 10 (depends on 1) The capacitance-to-digital converter according to claim 1, wherein the converter is realized as a sigma-delta modulator that comprises the interface circuit. ### Claim 11 A method for providing a digital output signal, comprising: providing an analog sensor signal by an input capacitor; generating a digital sensor signal by a converter as a function of the analog sensor signal; and providing a digital output signal by a calibration unit that is coupled to the converter, wherein the converter comprises an interface circuit that is coupled on its input side to the capacitor arrangement and comprises a first integrator having a first amplifier as well as a first and a second integrating capacitor, wherein the interface circuit comprises a first and a second chopping unit, such that the first chopping unit couples a first and a second input of the first amplifier to a first terminal of the first integrating capacitor, and the second chopping unit couples the first and the second input of the first amplifier to a first terminal of the second integrating capacitor. ### Claim 12 (depends on 11) The method according to claim 11, wherein the digital output signal has a polynomial dependency from an input signal of the calibration unit or a signal derived from the input signal. ### Claim 13 A capacitance-to-digital converter, comprising: a capacitor arrangement comprising an input capacitor; a converter that is coupled on its input side to the capacitor arrangement; and a calibration unit that is coupled on its input side to the converter, wherein the converter comprises an interface circuit that is coupled on its input side to the capacitor arrangement and comprises a first integrator having a first amplifier as well as a first and a second integrating capacitor, wherein the interface circuit comprises an input chopping unit that couples a first and a second input of the first amplifier to the capacitor arrangement, to a first terminal of the first integrating capacitor and to a first terminal of the second integrating capacitor, and wherein the capacitor arrangement is directly connected to the first terminal of the first integrating capacitor and to the first terminal of the second integrating capacitor.