# US 9,438,259 B2 · Circuit, an integrated circuit, a transmitter, a receiver, a transceiver, a method for generating a processed oscillator signal, an apparatus for generating a processed oscillator signal, and software-related implementations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,259 B2 - Document ID: US9438259B2 - Status: Granted - Kind: B2 - Application number: 14/832,342 - Filed: 2015-08-21 - Published: 2016-03-31 - Granted: 2016-09-06 - Earliest claimed: 2014-09-26 - Assignees: Intel IP Corporation - Applicants: Intel IP Corporation - Inventors: Stefan Tertinek; Peter Preyler; Thomas Mayer - Web page: https://patentgrep.com/patent/US9438259B2 ## CPC - H03M 1/10: Calibration or testing - G06F 1/0321: {Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers (G06F1/0314, G06F1/035 take precedence)} - H03L 7/00: Automatic control of frequency or phase; Synchronisation - H03M 1/82: with intermediate conversion to time interval - H03L 2207/50: All digital phase-locked loop - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique. ## Claims ### Claim 1 A circuit comprising: a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal; and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique, wherein the control circuit is configured to receive a frequency offset signal and to generate a plurality of polyphase signals, each polyphase signal corresponding to a phase shift with respect to the processed oscillator signal, wherein the control circuit is further configured to generate the control signal by combining the polyphase signals in the proper phase. ### Claim 2 (depends on 1) The circuit according to claim 1, wherein the control circuit is a fully digital circuit. ### Claim 3 A circuit comprising: a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal; and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique, wherein the control circuit comprises a plurality of at least partially cross-coupled polyphase circuits, each polyphase circuit being configured to generate a polyphase signal, and wherein the control circuit further comprises a multiplexer configured to combine the polyphase signals by multiplexing the plurality of polyphase signals to generate the control signal in the proper phase. ### Claim 4 (depends on 3) The circuit according to claim 3, wherein the multiplexer is configured to operate at a frequency of the processed oscillator signal, and wherein the plurality of the polyphase circuits is configured to operate at a frequency lower than the frequency of the processed oscillator signal. ### Claim 5 (depends on 4) The circuit according to claim 4, wherein the plurality of the polyphase circuits is configured to operate at a frequency being equal to the frequency of the processed oscillator signal divided by a total number of the polyphase circuits of the plurality of polyphase circuits. ### Claim 6 (depends on 3) The circuit according to claim 3, wherein the plurality of polyphase circuits comprises a plurality of polyphase component integrator circuits configured to receive a frequency offset signal and to integrate the received frequency offset signal to generate a plurality of polyphase component phase ramp signals, wherein the plurality of polyphase component integrator circuits form an integrator configured to integrate the frequency offset signal. ### Claim 7 (depends on 6) The circuit according to claim 6, wherein the plurality of polyphase component integrator circuits comprises a first polyphase component integrator circuit configured to generate a first polyphase component phase ramp signal of the plurality of polyphase component phase ramp signals and a second polyphase component integrator circuit configured to generate a second polyphase component phase ramp signal of the plurality of polyphase component phase ramp signals, wherein the first polyphase component integrator circuit comprises an adder configured to add the received frequency offset signal to the second polyphase component phase ramp signal. ### Claim 8 (depends on 7) The circuit according to claim 7, wherein the second polyphase component integrator circuit comprises an adder configured to add the received frequency offset signal to the first polyphase component phase ramp signal and a delay circuit to configured to delay an output of the adder of the second polyphase component integrator circuit by one clock cycle of a frequency of the polyphase circuits, wherein the delay circuit is configured to generate the second polyphase component phase ramp signal. ### Claim 9 (depends on 7) The circuit according to claim 7, wherein a first polyphase circuit of the plurality of polyphase circuits comprises the first polyphase component integrator circuit, and wherein a second polyphase circuit of the plurality of polyphase circuits comprises the second polyphase component integrator circuit. ### Claim 10 (depends on 1) The circuit according to claim 1, wherein the control circuit is configured to process a constant or quasi-constant frequency offset signal. ### Claim 11 (depends on 6) The circuit according to claim 6, wherein the plurality of polyphase circuits comprises a plurality of polyphase component correction circuits coupled to the plurality of polyphase component integrator circuits, wherein the plurality of polyphase component correction circuits is configured to receive the polyphase component phase ramp signals and to adjust the received polyphase component phase ramp signals to obtain the plurality of polyphase signals, wherein the plurality of polyphase component correction circuits is configured to correct non-linearities of the digital-to-time converter. ### Claim 12 (depends on 11) The circuit according to claim 11, wherein the plurality of polyphase component correction circuits comprise at least one look-up-table comprising data to correct the received polyphase component phase ramp signals based on calibration data of the digital-to-time converter. ### Claim 13 (depends on 6) The circuit according to claim 6, wherein the control circuit further comprises a time-interleaved noise shaping circuit configured to generate a plurality of polyphase component dither signals, and wherein the plurality of polyphase circuits further comprise a plurality of adders coupled to the plurality of polyphase component integrator circuits and configured to superimpose the plurality of polyphase component phase ramp signals with the plurality of polyphase component dither signals. ### Claim 14 (depends on 13) The circuit according to claim 13, wherein the time-interleaved noise shaping circuit is configured to receive the plurality of polyphase component phase ramp signals in the superimposed form and to generate the plurality of polyphase component dither signals based on the received polyphase component phase ramp signals in the superimposed form. ### Claim 15 (depends on 14) The circuit according to claim 14, wherein the time-interleaved noise shaping circuit comprises a plurality of polyphase component noise shaping circuits configured to generate the plurality of polyphase component dither signals, wherein the plurality of polyphase component noise shaping circuits form a noise shaper. ### Claim 16 (depends on 15) The circuit according to claim 15, wherein the plurality of polyphase component noise shaping circuits comprise a plurality of polyphase component filters, wherein the plurality of polyphase component filters form a noise shaping filter, wherein the plurality of polyphase component filters is configured to generate the plurality of polyphase component dither signals. ### Claim 17 (depends on 16) The circuit according to claim 16, wherein the plurality of polyphase component noise shaping circuits comprise a plurality of further polyphase component correction circuits configured to receive the plurality of polyphase component phase ramp signals in the superimposed form and to correct non-linearities of the digital-to-time converter in the received polyphase component phase ramp signals. ### Claim 18 (depends on 17) The circuit according to claim 17, wherein the plurality of further polyphase component correction circuits comprises at least one look-up-table comprising data to correct the received polyphase component phase ramp signals based on calibration data of the digital-to-time converter. ### Claim 19 A circuit comprising: a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal; a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique; and an oscillator configured to generate the oscillator signal, wherein the oscillator comprises a phase-locked loop circuit and a single reference oscillator circuit driving the phase-locked loop circuit. ### Claim 20 (depends on 19) The circuit according to claim 19, wherein the oscillator comprises a single phase-locked loop circuit or a plurality of phase-locked loop circuits driven by the single reference oscillator circuit. ### Claim 21 A transmitter, a receiver or a transceiver comprising a circuit, the circuit comprising: a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal; and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique, wherein the control circuit is configured to receive a frequency offset signal and to generate a plurality of polyphase signals, each polyphase signal corresponding to a phase shift with respect to the processed oscillator signal, wherein the control circuit is further configured to generate the control signal by combining the polyphase signals in the proper phase.