# US 9,438,258 B1 · Preamplifier, comparator and analog-to-digital converting apparatus including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,258 B1 - Document ID: US9438258B1 - Status: Granted - Kind: B1 - Application number: 14/816,955 - Filed: 2015-08-03 - Published: 2016-09-15 - Granted: 2016-09-06 - Earliest claimed: 2015-03-09 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Si-Wook Yoo - Web page: https://patentgrep.com/patent/US9438258B1 ## CPC - H03K 5/2481: {with at least one differential stage} - H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)} - H03F 3/45188: {Non-folded cascode stages} - H03M 1/145: {the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence)} - H03F 2200/312: the loading circuit of an amplifying stage comprising one or more switches - H03F 2203/45302: the common gate stage of a cascode dif amp being controlled - H03M 1/123: {Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters} - H03M 1/56: Input signal compared with linear ramp - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03F: AMPLIFIERS - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A preamplifier may include: a common active load suitable for providing output impedance; an output polarity changing unit suitable for changing an output polarity of output nodes; a multi-differential input stage suitable for receiving an input voltage, a coarse ramping voltage, a fine ramping voltage and a common mode voltage, and sampling the common mode voltage and the coarse ramping voltage for amplification operations; and a coupling blocking unit suitable for blocking a coupling between the output nodes and input nodes that are included in the multi-differential input stage. ## Claims ### Claim 1 A preamplifier comprising: a common active load suitable for providing output impedance; an output polarity changing unit suitable for changing an output polarity of output nodes; a multi-differential input stage suitable for receiving an input voltage, a coarse ramping voltage, a fine ramping voltage and a common mode voltage for differential amplification operations; and a coupling blocking unit suitable for blocking a coupling between the output nodes and the multi-differential input stage. ### Claim 2 (depends on 1) The preamplifier of claim 1, further comprising an inverter suitable for inverting a comparator enable signal, and transmitting an inverted comparator enable signal to the coupling blocking unit. ### Claim 3 (depends on 2) The preamplifier of claim 2, wherein the inverter uses the same voltage as a power supply voltage. ### Claim 4 (depends on 1) The preamplifier of claim 1, wherein the output polarity changing unit comprises first and second switches suitable for setting a first output as an output at a reset point, and changing the output from the first output to a second output before a comparison operation. ### Claim 5 (depends on 1) The preamplifier of claim 1, wherein the output polarity changing unit outputs a high state signal during coarse conversion, and outputs a low state signal during fine conversion. ### Claim 6 (depends on 1) The preamplifier of claim 1, wherein the coupling blocking unit comprises first and second cascode transistors that operate in a saturation region until the input voltage is compared. ### Claim 7 (depends on 1) The preamplifier of claim 1, wherein the multi-differential input stage samples a common mode voltage and a coarse ramping voltage based on a sampling control signal. ### Claim 8 (depends on 7) The preamplifier of claim 7, wherein the sampled coarse ramping voltage and the sampled common mode voltage have a differential relationship for the preamplifier. ### Claim 9 A comparator comprising: a preamplifier suitable for blocking a coupling between output and input nodes by changing an output polarity of the output nodes, sampling a common mode voltage and a coarse ramping voltage based on a sampling control signal, generating a coarse conversion result through the output node by amplifying a difference between an input voltage and the sampled coarse ramping voltage, and generating a fine conversion result through the output nodes by amplifying a difference between a fine ramping voltage and the sampled common mode voltage; and a signal processor suitable for generating the sampling control signal based on the coarse conversion result, and generating a comparison signal based on the coarse conversion result and the fine conversion result. ### Claim 10 (depends on 9) The comparator of claim 9, wherein the preamplifier comprises: a common active load suitable for providing output impedance; an output polarity changing unit suitable for changing the output polarity of the output node; a multi-differential input stage suitable for receiving the input voltage, the coarse ramping voltage, the fine ramping voltage and the common mode voltage and sampling the common mode voltage and the coarse ramping voltage; and a coupling blocking unit suitable for blocking the coupling between the output nodes and the multi-differential input stage. ### Claim 11 (depends on 10) The comparator of claim 10, wherein the preamplifier further comprises an inverter suitable for inverting a comparator enable signal, and transmitting the inverted comparator enable signal to the coupling blocking unit. ### Claim 12 (depends on 11) The comparator of claim 11, wherein the inverter uses the same voltage as a power supply voltage. ### Claim 13 (depends on 10) The comparator of claim 10, wherein the coupling blocking unit comprises first and second switches suitable for setting a first output as an output at a reset point, and changing the output from the first output to a second output before a comparison operation. ### Claim 14 (depends on 10) The comparator of claim 10, wherein the output polarity changing unit outputs a high state signal during coarse conversion, and outputs a low state signal during fine conversion. ### Claim 15 (depends on 10) The comparator of claim 10, wherein the coupling blocking unit comprises first and second cascode transistors that operate in a saturation region until the input voltage is compared. ### Claim 16 (depends on 9) The comparator of claim 9, wherein the sampled coarse ramping voltage and the sampled common mode voltage have a differential relationship for the preamplifier. ### Claim 17 (depends on 9) The comparator of claim 9, wherein the signal processor comprises: an amplifier suitable for amplifying the coarse conversion result and the fine conversion result; a controller suitable for generating the sampling control signal based on the coarse conversion result; and a selector suitable for selecting the coarse conversion result through the controller and the fine conversion result from the amplifier based on a select signal to output the comparison signal. ### Claim 18 (depends on 9) The comparator of claim 9, wherein the signal processor comprises: a controller suitable for generating the sampling control signal based on the coarse conversion result; and a selector suitable for selecting the coarse conversion result through the controller and the fine conversion result from the preamplifier based on a select signal to output the comparison signal. ### Claim 19 An analog-to-digital converting apparatus comprising: a preamplifier suitable for blocking a coupling between output and input nodes by changing an output polarity of the output nodes, sampling a common mode voltage and a coarse ramping voltage based on a sampling control signal, generating a coarse conversion result through the output nodes by amplifying a difference between an input voltage and the sampled coarse ramping voltage, and generating a fine conversion result through the output nodes by amplifying a difference between a fine ramping voltage and the sampled common mode voltage; a signal processor suitable for generating the sampling control signal based on the coarse conversion result, and generating a comparison signal based on the coarse conversion result and the fine conversion result; and a code decision unit suitable for deciding a coarse digital code and a fine digital code based on the comparison signal to output digital data. ### Claim 20 (depends on 19) The analog-to-digital converting apparatus of claim 19, wherein the preamplifier comprises: a common active load suitable for providing output impedance; an output polarity changing unit suitable for changing the output polarity of the output node; a multi-differential input stage suitable for receiving the input voltage, the coarse ramping voltage, the fine ramping voltage and the common mode voltage, and sampling the common mode voltage and the coarse ramping voltage; and a coupling blocking unit suitable for blocking the coupling between the output nodes and the multi-differential input stage.