# US 9,438,256 B2 · Slow to fast clock synchronization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,256 B2 - Document ID: US9438256B2 - Status: Granted - Kind: B2 - Application number: 14/478,387 - Filed: 2014-09-05 - Published: 2015-12-03 - Granted: 2016-09-06 - Earliest claimed: 2014-06-03 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Shane J. Keil; Gilbert H. Herbeck - Web page: https://patentgrep.com/patent/US9438256B2 ## CPC - H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence) - H03K 5/1534: Transition or edge detectors - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal. ## Claims ### Claim 1 An apparatus, comprising: a first flip-flop circuit configured to sample data dependent upon a first clock signal to generate sampled data; a synchronizer circuit configured to generate a synchronized first clock signal dependent upon a second clock signal, wherein at least one transition of the synchronized first clock signal corresponds to a transition of the second clock signal, wherein a frequency of the first clock signal is lower than a frequency of the second clock signal; an edge detection circuit configured to: detect an edge of the synchronized first clock signal; and assert an enable signal responsive to the detection of the edge of the synchronized first clock signal; and a second flip-flop circuit configured to capture, in response to the assertion of the enable signal, the sampled data dependent upon the second clock signal; wherein the synchronizer circuit comprises: a third flip-flop circuit configured to sample the first clock dependent upon the second clock signal; a fourth flip-flop circuit configured to sample an output of the third flip-flop circuit dependent upon the second clock signal. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the edge detection circuit includes one or more delay circuits. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the first flip-flop circuit comprises a D-type flip-flop circuit. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the synchronizer circuit further comprises a fifth flip-flop circuit configured to sample an output of the fourth flip-flop circuit dependent upon the second clock signal. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the edge detection circuit is further configured to detect a positive edge of the synchronized first clock signal dependent upon the output of the fourth flip-flop circuit and the output of the fifth flip-flop circuit. ### Claim 6 A method, comprising: receiving data from circuits included in a first clock domain; sampling the data dependent upon a clock signal included in the first clock domain to generate sampled data; synchronizing the clock signal included in the first clock domain to generate a synchronized clock signal, wherein at least one transition of the synchronized clock signal corresponds to a transition of a clock signal included in a second clock domain; wherein a frequency of the clock signal included in the first clock domain is lower than a frequency of the clock signal included in the second clock domain; detecting an edge of the synchronized clock signal included in the first clock domain; asserting an enable signal responsive to the detection of the edge of the synchronized clock signal; and capturing, in response to the assertion of the enable signal, the sampled data dependent upon the clock signal included in the second clock domain; wherein synchronizing the clock signal included in the first clock domain includes: sampling, using a first flip-flop circuit, the clock signal included in the first clock domain dependent upon the clock signal included in the second clock domain; and sampling, using a second flip-flop circuit, an output of the first flip-flop circuit dependent upon the clock signal included in the second clock domain. ### Claim 7 (depends on 6) The method of claim 6, wherein detecting the edge of the synchronized clock signal comprises delaying the synchronized clock signal. ### Claim 8 (depends on 6) The method of claim 6, wherein sampling the data dependent upon the clock signal included in the first clock domain comprises sampling the data using a third flip-flop circuit, wherein operation of the third flip-flop circuit is dependent upon the clock signal included in the first clock domain. ### Claim 9 (depends on 6) The method of claim 6, wherein capturing, in response to the assertion of the enable signal, the sampled data dependent upon the clock signal included in the second clock domain comprises capturing the sampled data using a third flip-flop circuit, wherein operation of the third flip-flop circuit is dependent upon the enable signal and the clock signal included in the second clock domain. ### Claim 10 (depends on 6) The method of claim 6, wherein synchronizing the clock signal included in the first clock domain comprises sampling, using a third flip-flop circuit, an output of the second flip-flop circuit dependent upon the clock signal included in the second clock domain. ### Claim 11 A system, comprising: a first circuit block using a first clock signal; and a second circuit block coupled the first circuit block and using a second clock signal, wherein the a frequency of the first block signal is lower than a frequency of the second clock signal, and wherein the second circuit block includes a synchronization unit configured to: sample data received from the first circuit block dependent upon a the first clock signal to generate sampled data; generate a synchronized first clock signal dependent upon the second clock signal, wherein at least one transition of the synchronized first clock signal corresponds to a transition of the second clock signal; detect an edge of the synchronized first clock signal; and assert an enable signal in response to the detection of the edge of the synchronized first clock signal; and capture, in response to the assertion of the enable signal, the sampled data dependent upon the second clock signal; wherein to generate the synchronized first clock signal, the synchronization unit is further configured to: sample the first clock dependent upon the second clock signal to generate a sampled first clock; and capture the sampled first clock dependent upon the second clock signal. ### Claim 12 (depends on 11) The system of claim 11, wherein to detect the edge of the synchronized first clock signal, the synchronization unit is further configured to delay the synchronized first clock signal. ### Claim 13 (depends on 11) The system of claim 11, wherein to sample the data received from the first circuit block, the synchronization unit is further configured to sample the data using a flip-flop circuit, wherein operation of the flip-flop circuit is dependent upon the first clock signal. ### Claim 14 (depends on 11) The system of claim 11, wherein to capture, in response to the assertion of the enable signal, the sampled data dependent the synchronization unit is further configured to capture the sampled data using a flip-flop circuit, wherein operation of the flip-flop circuit is dependent upon the enable signal and the second clock signal. ### Claim 15 (depends on 11) The system of claim 11, wherein the synchronization unit is further configured to capture the sampled first clock dependent upon the second clock signal to generate a captured clock signal. ### Claim 16 (depends on 15) The system of claim 15, wherein to generate the synchronized first clock signal, the synchronization unit is further configured to sample the captured clock signal dependent upon the second clock signal.