# US 9,438,252 B1 · Integrated circuits having low power, low interference and programmable delay generators therein and methods of operating same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,252 B1 - Document ID: US9438252B1 - Status: Granted - Kind: B1 - Application number: 14/887,663 - Filed: 2015-10-20 - Granted: 2016-09-06 - Earliest claimed: 2015-10-20 - Assignees: Integrated Device Technology, Inc. - Applicants: Integrated Device Technology, Inc. - Inventors: Chengming He; Ruben Eribes - Web page: https://patentgrep.com/patent/US9438252B1 ## CPC - H03L 7/0805: {the loop being adapted to provide an additional control signal for use outside the loop} - H03L 7/0991: {the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814)} - H03L 7/0995: {the oscillator comprising a ring oscillator} - H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A programmable delay generator includes a calibration circuit and a delay line responsive to a calibration control signal generated by the calibration circuit. The calibration circuit includes a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein. A frequency of the DCO is set by the calibration control signal. The delay line includes a second plurality of delay stages that are replicas of the first plurality of delay stages. The calibration circuit may include a current steering digital-to-analog converter (CSDAC), which is responsive to a digital calibration code, and a current-to-voltage converter, which is responsive to at least one current signal generated by the CSDAC. The DCO and other portions of the calibration circuit are disabled into a low power state upon completion of a calibration operation, which may commence upon start-up. ## Claims ### Claim 1 A programmable delay generator, comprising: a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit during a calibration operation; and a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit upon conclusion of the calibration operation when said DCO is powered-down into an inactive state. ### Claim 2 (depends on 1) The programmable delay generator of claim 1, wherein said calibration circuit comprises a current steering digital-to-analog converter (CSDAC) responsive to a digital calibration code and a current-to-voltage converter responsive to at least one current signal generated by said CSDAC; and wherein the current-to-voltage converter is active during the calibration operation and upon conclusion of the calibration operation when said DCO is powered-down into the inactive state. ### Claim 3 (depends on 2) The programmable delay generator of claim 2, wherein the current-to-voltage converter is responsive to a pair of current signals generated by said CSDAC, which remains active when said DCO is powered-down into the inactive state; wherein a magnitude of the pair of analog current signals remains constant during calibration of said DCO; and wherein the first and second control signals are equivalent. ### Claim 4 (depends on 1) The programmable delay generator of claim 1, wherein said DCO is configured as a ring oscillator. ### Claim 5 (depends on 1) The programmable delay generator of claim 1, wherein said DCO is configured as a ring oscillator having N delay stages therein; and wherein said delay line has M stages therein, where N and M are positive integers and M is greater than N. ### Claim 6 (depends on 1) The programmable delay generator of claim 1, wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO during the calibration operation; and wherein the periodic signal is disabled upon conclusion of the calibration operation. ### Claim 7 (depends on 1) The programmable delay generator of claim 1, wherein said calibration circuit comprises a non-monotonic digital-to-analog converter (DAC). ### Claim 8 A programmable delay generator, comprising: a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit; and a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit; wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO; and wherein the frequency comparator is configured to generate a varying multi-bit digital calibration code during a calibration operation and store a final digital calibration code upon completion of the calibration operation. ### Claim 9 A programmable delay generator, comprising: a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit; and a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit; wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO; and wherein said calibration circuit comprises a feedback divider configured to generate the periodic feedback signal in response to the periodic signal generated by said DCO during a calibration operation; and wherein said DCO and the feedback divider are disabled into a low power state upon completion of the calibration operation. ### Claim 10 A programmable delay generator, comprising: a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit; and a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit; wherein said calibration circuit comprises a current steering digital-to-analog converter (CSDAC) responsive a digital calibration code and a current-to-voltage converter responsive to at least one current signal generated by said CSDAC; and wherein said calibration circuit further comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO, said frequency comparator configured to generate the digital calibration code as a varying code during a calibration operation and store a final digital calibration code upon completion of the calibration operation. ### Claim 11 (depends on 10) The programmable delay generator of claim 10, wherein frequency comparison operations within said frequency comparator are terminated and said DCO is disabled into a low power state upon completion of the calibration operation. ### Claim 12 A programmable delay generator, comprising: a calibration circuit comprising a digitally-controlled oscillator (DCO) having a frequency set by a first control signal generated by said calibration circuit during a calibration operation when said DCO is active; and a delay line having a plurality of delay stages therein that are responsive to a second control signal generated by said calibration circuit upon completion of the calibration operation when said DCO is inactive. ### Claim 13 (depends on 12) The programmable delay generator of claim 12, wherein said DCO comprises a plurality of delay stages therein that are replicas of the plurality of delay stages in said delay line. ### Claim 14 (depends on 13) The programmable delay generator of claim 13, wherein said DCO is configured as a ring oscillator; and wherein said calibration circuit comprises a feedback divider responsive a periodic signal generated by the ring oscillator. ### Claim 15 (depends on 14) The programmable delay generator of claim 14, wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal generated by the feedback divider; and wherein the frequency comparator and feedback divider are disabled into respective low power states upon completion of the calibration operation. ### Claim 16 (depends on 15) The programmable delay generator of claim 15, wherein said calibration circuit comprises a current steering digital-to-analog converter (CSDAC) responsive a digital calibration code generated by the frequency comparator; and wherein the CSDAC remains active during the calibration operation and post completion of the calibration operation. ### Claim 17 (depends on 16) The programmable delay generator of claim 16, wherein a magnitude of a current generated by the CSDAC controls a frequency of the periodic signal generated by the ring oscillator during the calibration operation and controls a delay provided by the plurality of delay stages within the delay line post completion of the calibration operation.