# US 9,438,251 B2 · Clock generating circuit, semiconductor device including the same, and data processing system

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- Number: US 9,438,251 B2
- Document ID: US9438251B2
- Status: Granted
- Kind: B2
- Application number: 14/679,450
- Filed: 2015-04-06
- Published: 2015-07-30
- Granted: 2016-09-06
- Earliest claimed: 2009-09-09
- Assignees: PS4 Luxco S.a.r.l.
- Applicants: Ps4 Luxco S.A.R.L.
- Inventors: Kazutaka Miyano
- Web page: https://patentgrep.com/patent/US9438251B2

## CPC

- H03L 7/0818: {the controlled phase shifter comprising coarse and fine delay or phase-shifting means}
- G11C 7/1066: {Output synchronization}
- G11C 7/1093: {Input synchronization}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- H03L 7/0802: {the loop being adapted for reducing power consumption (H03L7/14 takes precedence)}
- H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)}
- H03L 7/0814: {the phase shifting device being digitally controlled}
- H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input}
- H03L 7/095: using a lock detector (H03L7/087 takes precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for generating an internal clock signal by a clock generating circuit, including generating the internal clock signal based on an external clock signal, adjusting a phase of the internal clock signal by using a phase control value to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal, switching operation modes including a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value, and the switching includes switching from the second operation mode to the first operation mode in response to a trigger signal.

## Claims

### Claim 1

A method for generating an internal clock signal by a clock generating circuit, comprising:
generating the internal clock signal based on an external clock signal;
adjusting a phase of the internal clock signal by using a phase control value to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal; and
switching operation modes including a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value,
wherein the switching includes switching from the second operation mode to the first operation mode in response to a trigger signal, and
the switching includes switching from the first operation mode to the second operation mode in response to a state where the internal clock signal attains a predetermined phase;
wherein the trigger signal is generated in response to an output signal of a power detecting circuit, and wherein the power detecting circuit outputs a first level of the output signal when a power supply voltage varies equal to or higher than a reference acceleration and outputs a second level of the output signal when the power supply voltage varies smaller than the reference acceleration, the first and second levels being different from each other.

### Claim 2 (depends on 1)

The clock generating circuit as claimed in claim 1, wherein the trigger signal is activated at the time of a refresh operation that restores information in a memory cell is performed.

### Claim 3 (depends on 2)

The clock generating circuit as claimed in claim 2, wherein the switching includes switching from the second operation mode to the first operation mode after the refresh operation is completed.

### Claim 4 (depends on 1)

The method for generating an internal clock signal as claimed in claim 1, further comprising:
outputting an output signal to outside in synchronization with the internal clock signal by an output buffer,
wherein the clock generating circuit includes:
a replica circuit that generates a feedback clock signal from the internal clock signal, the feedback clock signal being supplied to the phase-controlling unit; and
the replica circuit has a substantially same circuit configuration as the output buffer.

### Claim 5 (depends on 1)

The method for generating an internal clock signal as claimed in claim 1, wherein the trigger signal is output by a logic circuit which includes a first input node configured to receive the output signal of the power detecting circuit and a second input node configured to receive a refresh signal.

### Claim 6 (depends on 1)

The method for generating an internal clock signal as claimed in claim 1, wherein the trigger signal is output by a logic circuit which includes a first input node configured to receive the output signal of the power detecting circuit and a second input node configured to receive an output of a timer circuit.

### Claim 7

A method for generating a clock by a clock generating circuit comprising:
receiving a first clock signal and a first control signal and outputting a second clock signal;
comparing the second clock signal with the first clock signal and outputting a comparison signal; and
receiving the comparison signal and sending the first control signal to control the outputting the second clock signal,
wherein the clock generating circuit is controlled by a control circuit outputting a second control signal, the second control signal being output in response to at least a first detection signal that is generated when a first variation of a power supply voltage has been detected; and
the detection signal is generated by a detecting circuit, the detecting circuit including:
first, second and third resistor circuits each coupled between a power supply and a ground;
a first comparator including a first input node coupled to the first resistor circuit and a second input node coupled to the third resistor circuit, and including an output node;
a second comparator including a first input node coupled to the third resistor circuit and the second resistor circuit, and including an output node; and
an AND gate including a first input node coupled to the output node of the first comparator and the second input node coupled to the output node of the second comparator, and the AND gate outputting an output signal of the detecting circuit.

### Claim 8 (depends on 7)

The method for generating a clock as claimed in claim 7, wherein the second control signal is further output in response to a second detection signal that is generated when a first time period elapse of deactivation of the clock generating circuit has been detected.

### Claim 9 (depends on 7)

The method for generating a clock as claimed in claim 7, wherein the control circuit further includes:
a logic circuit receiving the first detection signal output from the detecting circuit that detects the first variation of the power supply voltage of the device and an additional signal, and the logic circuit outputting the second control signal,
wherein the additional signal is one of a refresh signal that is generated in a refresh operation and a timer signal that is generated when a first time period elapse of deactivation of the clock generating circuit has been detected.

### Claim 10 (depends on 7)

The method for generating a clock as claimed in claim 7, wherein the detecting circuit detects a variation of the power supply voltage of the device,
wherein the detecting circuit generating a first level of the first detection signal when it is detected that a variation of the power supply voltage of the device is equal to or higher than the first variation, and the detecting circuit further generating a second level of the first detection signal when it is detected that a variation of the power supply voltage of the device is smaller than the first variation, the first and second level being different from each other.

### Claim 11 (depends on 7)

The method for generating a clock as claimed in claim 7, wherein the first resistor circuit of the detecting circuit comprises:
a first resistor coupled between the power supply and a first intermediate node; and
a second resistor coupled between the first intermediate node and the ground, wherein the first intermediate node being coupled to the first input node of the first comparator,
wherein the second resistor circuit of the detecting circuit comprises:
a third resistor coupled between the power supply and a second intermediate node;
a fourth resistor coupled between the second intermediate node and the ground,
the second intermediate node being coupled to the second input node of the second comparator;
wherein the third resistor circuit of the detecting circuit comprises:
a fifth resistor coupled between the power supply and a third intermediate node;
a sixth resistor coupled between the third intermediate node and the ground, the third intermediate being coupled to the second input node of the first comparator and the first input node of the second comparator; and
wherein the first and fourth resistors are the substantially same in a resistance value as each other,
wherein the second and third resistors are the substantially same in a resistance value as each other, and
wherein each of the fifth and sixth resistors is smaller in a resistance value than each of the first, second, third, and fourth resistors.

### Claim 12 (depends on 7)

The method for generating a clock as claimed in claim 7, wherein the clock generating circuit is controlled so as to change from deactivation to activation in response to the first detection signal.

### Claim 13

A method for generating a clock comprising:
receiving a first clock signal and outputting a second clock signal;
comparing the second clock signal with the first clock signal to change, when activated, a delay of the second clock signal;
supplying a first voltage to a first voltage line;
supplying a second voltage to a second voltage line; and
detecting a variation in voltage according to an acceleration of a variation of a power supply voltage by a voltage detecting circuit; and
the voltage detecting circuit activating the phase control circuit in response to the detecting thereof.

### Claim 14 (depends on 13)

The method for generating a clock according to claim 13, further comprising:
counting a first cycle by a timer circuit, wherein the timer circuit activating the phase control circuit in response to the counting of the first cycle.

### Claim 15 (depends on 13)

The method for generating a clock according to claim 13, wherein when the power supply voltage varies at an acceleration equal to or greater than a predetermined acceleration, a detection signal outputted by the voltage detecting circuit is activated to a low level.

### Claim 16 (depends on 13)

The method for generating a clock according to claim 13, wherein the voltage detecting circuit includes a plurality of resistors including a first and a second resistor substantially greater than the resistance values of a third resistor.