# US 9,438,250 B2 · Variable rate interpolation with numerically controlled oscillator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,250 B2 - Document ID: US9438250B2 - Status: Granted - Kind: B2 - Application number: 14/483,415 - Filed: 2014-09-11 - Published: 2016-03-17 - Granted: 2016-09-06 - Earliest claimed: 2014-09-11 - Assignees: Hughes Network Systems, LLC - Applicants: Hughes Network Systems, LLC - Inventors: Santharam Gurumani; Bala Subramniam - Web page: https://patentgrep.com/patent/US9438250B2 ## CPC - H03L 7/00: Automatic control of frequency or phase; Synchronisation - G06F 1/022: {Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers (G06F1/025, G06F1/03 take precedence)} - G06F 1/08: Clock generators with changeable or programmable clock frequency - H03L 7/0994: {comprising an accumulator} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A numerically controlled oscillator includes a phase accumulator that outputs a phase word and a clock that periodically outputs a clock signal in accordance with a delay interval. The phase accumulator outputs a new phase word in response to receiving the clock signal. A clock controller calculates a timing drift and adjusts the delay interval to reduce the timing drift. A method includes receiving a plurality of frequency control words, calculating a delay interval, accumulating the frequency control words in accordance with the delay interval to generate a phase word, converting the phase word to a waveform, calculating a timing drift, and adjusting the delay interval to reduce the timing drift. ## Claims ### Claim 1 A numerically controlled oscillator comprising: a phase accumulator configured to output a phase word; a clock configured to periodically output a variable clock signal in accordance with a delay interval, wherein the phase accumulator is configured to output a new phase word in response to receiving the clock signal; and a clock controller programmed to calculate a timing drift from a ratio of an output sample rate to an input sample rate and adjust a length of the delay interval of the variable clock signal to reduce the calculated timing drift, wherein the clock controller is programmed to adjust the length of the delay interval of the variable clock signal to a rate calculated from the calculated timing drift. ### Claim 2 (depends on 1) The numerically controlled oscillator of claim 1, wherein the clock controller is configured to set the delay interval. ### Claim 3 (depends on 1) The numerically controlled oscillator of claim 1, wherein the clock controller is configured to output a delay signal representing the delay interval. ### Claim 4 (depends on 1) The numerically controlled oscillator of claim 1, wherein the clock controller is configured to compare the ratio to a predetermined threshold. ### Claim 5 (depends on 4) The numerically controlled oscillator of claim 4, wherein the clock controller is configured to adjust the delay interval to reduce the timing drift if the ratio exceeds the predetermined threshold. ### Claim 6 (depends on 1) The numerically controlled oscillator of claim 1, further comprising a phase-to-amplitude converter configured to generate a waveform in accordance with the phase word output by the phase accumulator. ### Claim 7 (depends on 1) The numerically controlled oscillator of claim 1, wherein the phase word includes an accumulation of frequency control words received by the phase accumulator. ### Claim 8 (depends on 1) The numerically controlled oscillator of claim 1, wherein the phase accumulator includes a digital input module configured to receive a first frequency control word. ### Claim 9 (depends on 8) The numerically controlled oscillator of claim 8, wherein the phase accumulator further includes a summation block configured to receive the first frequency control word from the digital input module and output a first phase word. ### Claim 10 (depends on 9) The numerically controlled oscillator of claim 9, wherein the phase accumulator includes a delay block configured to receive the first phase word from the summation block and output the first phase word to the summation block in response to receiving the clock signal. ### Claim 11 (depends on 10) The numerically controlled oscillator of claim 10, wherein the summation block is configured to add the first phase word to a second frequency control word and output a second phase word. ### Claim 12 A method comprising: receiving a plurality of frequency control words in accordance with a variable clock signal; calculating, via a clock controller, a delay interval of the variable clock signal; accumulating the frequency control words in accordance with the delay interval to generate a phase word; converting the phase word to a waveform; calculating a timing drift from a ratio of an output sample rate to an input sample rate; and adjusting a length of the delay interval of the variable clock signal to reduce the calculated timing drift, wherein adjusting the length of the delay interval includes adjusting the length of the delay interval to a rate calculated from the calculated timing drift. ### Claim 13 (depends on 12) The method of claim 12, wherein calculating the timing drift includes comparing the ratio to a predetermined threshold. ### Claim 14 (depends on 13) The method of claim 13, wherein the delay interval is adjusted if the ratio exceeds the predetermined threshold. ### Claim 15 A numerically controlled oscillator comprising: a phase accumulator having a digital input module configured to receive a plurality of control words, a summation block configured to output a phase word representing an accumulation of the plurality of frequency control words, and a delay block configured to provide the accumulation of the plurality of frequency control words to the summation block; a clock configured to periodically output a variable clock signal in accordance with a delay interval, wherein the phase accumulator is configured to output the accumulation of frequency control words in response to receiving the clock signal; and a clock controller programmed to calculate a timing drift from a ratio of an output sample rate to an input sample rate and adjust a length of the delay interval to reduce the calculated timing drift, wherein the clock controller is programmed to adjust the length of the delay interval of the variable clock signal to a rate calculated from the calculated timing drift. ### Claim 16 (depends on 15) The numerically controlled oscillator of claim 15, wherein the clock controller is configured to compare the ratio to a predetermined threshold. ### Claim 17 (depends on 16) The numerically controlled oscillator of claim 16, wherein the clock controller is configured to adjust the delay interval to reduce the timing drift if the ratio exceeds the predetermined threshold.