Low power digital self-gated binary counter

An n-bit counter circuit, comprising:

• a plurality of cascaded counter sub-modules including at least first and second cascaded counter sub-modules, the first counter sub-module being at least a lower-order counter sub-module relative to the second counter sub-module, the second counter sub-module being a higher-order counter sub-module relative to the first counter sub-module, as well as being a lower-order counter sub-module relative to subsequent cascaded counter sub-modules;
• and
• control logic coupled to the first counter sub-module, wherein:
• the control logic includes a clock-gating integrated cell (CGIC) that clocks at least the second counter sub-module dependent on a logical combination of outputs of at least the first counter sub-module, and provides a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules dependent on a logical combination of the outputs of at least the second counter sub-module;
• and
• the control logic does not include any intervening memory device between the first counter sub-module and the CGIC for use in resolution of a logical combination of outputs,
• wherein:
• the CGIC is coupled between the first counter sub-module and the second counter sub-module and controls a clock input of the second counter sub-module;
• the CGIC comprises a latch having an output operatively coupled to a first input of a two-input AND gate, wherein:
• the latch is operated by a changing level of a clock signal;
• the clock signal is operatively coupled to a second input of the two-input AND gate;
• and
• an input to the latch is a logically ANDed output of the first counter sub-module.