# US 9,438,247 B2 · Apparatus for simplification of input signal

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- Number: US 9,438,247 B2
- Document ID: US9438247B2
- Status: Granted
- Kind: B2
- Application number: 14/567,816
- Filed: 2014-12-11
- Published: 2015-06-25
- Granted: 2016-09-06
- Earliest claimed: 2013-12-19
- Assignees: Lsis Co., Ltd.
- Applicants: Lsis Co., Ltd.
- Inventors: Kang Hee Park
- Web page: https://patentgrep.com/patent/US9438247B2

## CPC

- H03K 21/026: {comprising logic circuits}
- H03K 5/1534: Transition or edge detectors
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The present disclosure relates to an apparatus for simplification of input signal configured to simplify a process of microprocessor and to enhance a speed by transforming six input modes of 1-phase/2-input/1-multiplication mode, 1-phase/2-input/2-multiplication mode, CW/CCW mode, 2-phase/1-multiplication mode, 2-phase/2-multiplication mode and 2-phase/4-multiplication mode to a same shape according to types of encoder connected to a PLC high speed counter, and transmitting to the microprocessor, and by adding the six types of input modes to a logic gate circuit of a high speed counter input circuit.

## Claims

### Claim 1

An apparatus for simplification of input signal configured to input, to an MPU (Micro Processing Unit), an output of an input circuit at a PLC high speed counter module by converting the input to a single signal, the apparatus comprising:
a first detector configured to output a single pulse in response to a rising edge or a falling edge by detecting the rising edge or the falling edge of a reference signal, which is a reference of adding or deducting calculation in response to an operation mode of the high speed counter module;
a second detector configured to detect, from an output of the first detector, a pulse of rising edge or falling edge configured to perform an actual adding or deducting calculation in response to an operation mode of the high speed counter module; and
a switching unit configured to output an output of the second detector using the adding or deducting calculation.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein a control signal is transmitted to the first, second detectors and the switching unit by using a general output port of the MPU.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the operation mode includes any one mode of a first mode of 1-phase/2-input/1-multiplication method, a second mode of 1-phase/2-input/2-multiplication method, a third mode of CW/CCW method, a fourth mode of 2-phase/1-multiplication method, a fifth mode of 2-phase/2-multiplication method and a sixth mode of 2-phase/4-multiplication method.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the switching unit includes a 2-bit switch configured to perform a one-on-one connection or a cross connection in response to a control signal by receiving a 2-bit input, and a switch controller configured to control the 2-bit switch by outputting through adding or deducting calculation in response to the operation mode.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first detector includes a first oscillation unit configured to output a signal pulse by detecting a rising edge of a first input, a second oscillation unit configured to output a signal pulse by detecting a falling edge of a first input, a third oscillation unit configured to output a signal pulse by detecting a rising edge of a second input, a fourth oscillation unit configured to output a signal pulse by detecting a falling edge of a second input, and an edge detector configured to detect only an output of a reference signal from the first to fourth oscillation units in response to the operation mode.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the edge detector removes an input which is not a reference signal in response to the operation mode.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the edge detector combines outputs corresponding to the reference signal in response to the operation mode.