# US 9,438,244 B2 · Circuits for and methods of controlling power within an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,244 B2 - Document ID: US9438244B2 - Status: Granted - Kind: B2 - Application number: 14/526,192 - Filed: 2014-10-28 - Published: 2016-04-28 - Granted: 2016-09-06 - Earliest claimed: 2014-10-28 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Santosh Kumar Sood; Brian C. Gaide; Steven P. Young - Web page: https://patentgrep.com/patent/US9438244B2 ## CPC - H03K 19/17784: for supply voltage - H03K 19/0008: {Arrangements for reducing power consumption} - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed. ## Claims ### Claim 1 A circuit for controlling power within an integrated circuit, the circuit comprising: a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks, wherein each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input configured to receive a reference voltage and a second input configured to receive the global control signal; wherein each power control block further comprises a selection circuit having a first input configured to receive the global control signal, a second input configured to receive a second control signal, and a third input configured to receive a power control signal; wherein the global control signal when selected enables, for each circuit block, a coupling of the reference voltage to a first input of the corresponding circuit block; and wherein the power control signal enables, for each circuit block, a selection of the global control signal or the second control signal to enable an operating mode of the circuit block. ### Claim 2 (depends on 1) The circuit of claim 1, wherein variable delay in the coupling of the global control signal to inputs of the plurality of power control blocks enables a staggered power-up of the plurality of circuit blocks. ### Claim 3 (depends on 1) The circuit of claim 1, wherein: each power control block comprises a switch having a control terminal configured to receive the global control signal when selected; and the switch enables the coupling of the reference voltage to the corresponding circuit block. ### Claim 4 (depends on 1) The circuit of claim 1, wherein the second control signal comprises a user-generated signal. ### Claim 5 (depends on 4) The circuit of claim 4, wherein the user-generated signal comprises a static control signal. ### Claim 6 (depends on 1) The circuit of claim 1, wherein each power control block is further configured to receive an enable signal for enabling the coupling of the reference voltage to the plurality of circuit blocks during a power-up phase. ### Claim 7 A circuit for controlling power within an integrated circuit, the circuit comprising: a plurality of circuit blocks; a plurality of control signals including a global control signal that is routed within the integrated circuit; and a plurality of power control blocks, wherein each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a selection circuit having a first input configured to receive the global control signal, a second input configured to receive a second control signal of the plurality of control signals, and a third input configured to receive a power control signal; wherein variable delay in the routing of a reference voltage to the plurality of circuit blocks enables a staggered power-up of the plurality of circuit blocks when the global control signal is selected by the selection circuits of the power control blocks; and wherein the power control signal enables, for each circuit block, a selection of the global control signal or the second control signal to enable an operating mode of the circuit block. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the plurality of circuit blocks comprise configurable logic blocks. ### Claim 9 (depends on 7) The circuit of claim 7, wherein: each power control block comprises a switch having a control terminal coupled to a control signal; and the control signal enables coupling the reference voltage to the circuit block. ### Claim 10 (depends on 7) The circuit of claim 7, wherein the second control signal comprises a user generated signal. ### Claim 11 (depends on 10) The circuit of claim 10, wherein the user-generated signal comprises a user control signal. ### Claim 12 (depends on 10) The circuit of claim 10, wherein the user-generated signal comprises a static control signal. ### Claim 13 (depends on 7) The circuit of claim 7, wherein each power control block is further configured to receive an enable signal for enabling the coupling of the reference voltage during a power-up of the plurality of circuit blocks. ### Claim 14 A method of controlling power within an integrated circuit, the method comprising: providing a plurality of circuit blocks; routing a global control signal within the integrated circuit; coupling each circuit block of the plurality of circuit blocks to a corresponding power control block of a plurality of power control blocks, coupling, for each power control block of the plurality of circuit blocks, a reference voltage to a first input of the power control block; coupling, for each power control block, the global control signal to a second input of the power control block; implementing, for each power control block, a selection circuit having a first input configured to receive the global control signal, a second input configured to receive a second control signal, and a third input configured to receive a power control signal, wherein the power control signal enables, for each circuit block, a selection of the global control signal or the second control signal to enable an operating mode of the circuit block; and coupling, for each circuit block of the plurality of circuit blocks, the reference voltage to the corresponding circuit block in response to a selection of the global control signal. ### Claim 15 (depends on 14) The method of claim 14, wherein the coupling of the reference voltage to the corresponding circuit blocks comprises comprising providing a staggered power-up of the plurality of circuit blocks. ### Claim 16 (depends on 14) The method of claim 14, further comprising coupling, for each power control block, a control signal to a control terminal of a switch, the control signal enabling the coupling of the reference voltage to the corresponding circuit block. ### Claim 17 (depends on 14) The method of claim 14, wherein implementing a selection circuit comprises coupling a user generated signal to the second input. ### Claim 18 (depends on 14) The method of claim 14, further comprising coupling, for each power control block, an enable signal for enabling the coupling of the reference voltage during a power up-phase.