# US 9,438,243 B2 · Programmable logic circuit and nonvolatile FPGA

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- Number: US 9,438,243 B2
- Document ID: US9438243B2
- Status: Granted
- Kind: B2
- Application number: 14/983,968
- Filed: 2015-12-30
- Published: 2016-04-21
- Granted: 2016-09-06
- Earliest claimed: 2014-01-27
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Shinichi Yasuda; Kosuke Tatsumura; Mari Matsumoto; Koichiro Zaitsu; Masato Oda
- Web page: https://patentgrep.com/patent/US9438243B2

## CPC

- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- H03K 19/018585: {programmable}
- H03K 19/0948: using CMOS {or complementary insulated gate field-effect transistors}
- H03K 19/177: arranged in matrix form
- H03K 19/1776: for memories
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.

## Claims

### Claim 1

A programmable logic circuit comprising:
a plurality of first wiring lines;
a plurality of second wiring lines intersecting with the first wiring lines in intersecting areas;
a plurality of cells disposed in the intersecting areas, at least one of the cells including a programmable device with a first terminal and a second terminal, the first terminal of the programmable device being connected to one of the first wiring lines, and the second terminal being connected to one of the second wiring lines;
a plurality of first cut-off transistors each including a source and a drain, one of the source and the drain being connected to the one of the second wiring lines; and
a plurality of first CMOS inverters each corresponding to one of the first cut-off transistors, each of the first CMOS inverters including an input terminal, the input terminal being connected to the other of the source and the drain of the corresponding one of the first cut-off transistors,
wherein at most one of the programmable devices connected to one of the second wiring lines is programmed.

### Claim 2 (depends on 1)

The circuit according to claim 1, wherein if the programmable device is to be programmed, a drive voltage Vdd is applied to a gate of one of the first cut-off transistors.

### Claim 3 (depends on 2)

The circuit according to claim 2, wherein a voltage Vpp used to program the programmable device is in a range
Vdd<Vpp<2.0×109×Tox+Vdd
where Tox is a thickness of a gate insulating film of each of the first cut-off transistors.

### Claim 4 (depends on 1)

The circuit according to claim 1, wherein the programmable device is a MOS transistor, one of the first terminal and the second terminal of the programmable device is a gate of the MOS transistor, and the other is at least one of a source and a drain of the MOS transistor.

### Claim 5 (depends on 1)

The circuit according to claim 1, wherein the programmable device is a resistive change memory including a first electrode, a second electrode, and a resistive change layer disposed between the first electrode and the second electrode.

### Claim 6 (depends on 1)

The circuit according to claim 1, further comprising:
a plurality of first transistors corresponding to the first cut-off transistors, each of the first transistors including a source and a drain, one of the source and the drain being connected to a gate of the corresponding one of the first cut-off transistors;
a third wiring line to which the other of the source and the drain of each first transistor is connected; and
a fourth wiring line to which a gate of each first transistor is connected.

### Claim 7 (depends on 1)

The circuit according to claim 1, further comprising:
a plurality of diodes each corresponding to one of the first cut-off transistors, a cathode of each diode being connected to a gate of the corresponding one of the first cut-off transistors; and
a third wiring line to which an anode of each diode is connected.

### Claim 8 (depends on 1)

The circuit according to claim 1, further comprising second CMOS inverters each corresponding to one of the first wiring lines to drive the corresponding one of the first wiring lines.

### Claim 9 (depends on 8)

The circuit according to claim 8, further comprising a plurality of second cut-off transistors each connected between an output of a corresponding one of the second CMOS inverters and a corresponding one of the first wiring lines.

### Claim 10 (depends on 9)

The circuit according to claim 9, further comprising a plurality of second transistors each corresponding to one of the second wiring lines, one of a source and a drain of each second transistor being connected to the corresponding one of the second wiring lines on an opposite side to the first cut-off transistor connected to the corresponding one of the second wiring lines.

### Claim 11 (depends on 10)

The circuit according to claim 10, further comprising a plurality of third transistors each corresponding to one of the first wiring lines, one of a source and a drain of each third transistor being connected to the corresponding one of the first wiring lines on an opposite side to the second cut-off transistor connected to the corresponding one of the first wiring lines.

### Claim 12 (depends on 1)

A nonvolatile FPGA comprising a plurality of unit blocks, at least one of the unit blocks including:
a logic block that performs a logical operation; and
a switching block that controls connection and disconnection between adjacent ones among the unit blocks and controls connection and disconnection with the logic block,
at least one of the logic block and the switching block including the programmable logic circuit according to claim 1.

### Claim 13

A programmable logic circuit comprising:
a plurality of first wiring lines;
a plurality of second wiring lines intersecting with the first wiring lines in intersecting areas;
a plurality of cells disposed in the intersecting areas, at least one of the cells including a programmable device with a first terminal and a second terminal, the first terminal of the programmable device being connected to one of the first wiring lines, and the second terminal being connected to one of the second wiring lines;
a plurality of first cut-off transistors each including a source and a drain, one of the source and the drain being connected to the one of the second wiring lines;
a plurality of first CMOS inverters each corresponding to one of the first cut-off transistors, each of the first CMOS inverters including an input terminal, the input terminal being connected to the other of the source and the drain of the corresponding one of the first cut-off transistors; and
a plurality of first transistors each corresponding to one of the second wiring lines, one of a source and a drain of each first transistor being connected to the corresponding one of the second wiring lines on an opposite side to the first cut-off transistor connected to the corresponding one of the second wiring lines.

### Claim 14 (depends on 13)

The circuit according to claim 13, wherein the programmable device is a MOS transistor, one of the first terminal and the second terminal of the programmable device is a gate of the MOS transistor, and the other is at least one of a source and a drain of the MOS transistor.

### Claim 15 (depends on 13)

The circuit according to claim 13, wherein the first transistors are p-channel MOS transistors.

### Claim 16 (depends on 13)

The circuit according to claim 13, further comprising second CMOS inverters each corresponding to one of the first wiring lines to drive the corresponding one of the first wiring lines.

### Claim 17

A programmable logic circuit comprising:
a plurality of first wiring lines;
a plurality of second wiring lines intersecting with the first wiring lines in intersecting areas;
a plurality of cells disposed in the intersecting areas, at least one of the cells including a programmable device with a first terminal and a second terminal, the first terminal of the programmable device being connected to one of the first wiring lines, and the second terminal being connected to one of the second wiring lines;
a plurality of first cut-off transistors each including a source and a drain, one of the source and the drain being connected to the one of the second wiring lines;
a plurality of first CMOS inverters each corresponding to one of the first cut-off transistors, each of the first CMOS inverters including an input terminal, the input terminal being connected to the other of the source and the drain of the corresponding one of the first cut-off transistors; and
a plurality of first transistors each corresponding to one of the first wiring lines, one of a source and a drain of each first transistor being connected to the corresponding one of the first wiring lines.

### Claim 18 (depends on 17)

The circuit according to claim 17, wherein the programmable device is a MOS transistor, one of the first terminal and the second terminal of the programmable device is a gate of the MOS transistor, and the other is at least one of a source and a drain of the MOS transistor.

### Claim 19 (depends on 17)

The circuit according to claim 17, wherein the first transistors are n-channel MOS transistors.

### Claim 20 (depends on 17)

The circuit according to claim 17, further comprising second CMOS inverters each corresponding to one of the first wiring ones to drive the corresponding one of the first wiring lines.