Low-power digital logic using a Boolean logic switched inductor-capacitor (SLC) circuit
AssigneeRaytheon Company
InventorsHarry B. Marr, Kenneth E. Prager, Julia L. Karl, Daniel Thompson
Life of this patent
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Abstract
A low-power digital logic architecture exhibits the same logic and voltage level behavior as standard digital logic. A logic switch and a pair of unidirectional switches are used to control the direction of charge flow in a switched-inductor capacitor (SLC) circuit, allowing the inductor to pull charge back-and-forth from one side of the load capacitor to the other to both switch the logical state at the top of the capacitor and to recycle and store the charge in the capacitor itself.
Claims16
A low-power digital logic circuit, comprising:
- a switched inductor-capacitor (SLC) circuit comprising a load capacitor, an inductor and a pair of unidirectional switches configured to switch in opposition to allow charge to flow either in a clockwise direction or a counter clockwise direction around the circuit, and a logic switch that implements a Boolean logic function, said logic switch responsive to a first logical input to configure the unidirectional switches to select the direction of charge flow, said inductor pulling charge from one side of the load capacitor to the other side of the load capacitor to switch a logical output at the top of the load capacitor, said unidirectional switches trapping charge on either side of the load capacitor to hold the logical output and prevent oscillation of the SLC circuit.
A low-power digital logic circuit, comprising:
- a first logical input;
- a logical output;
- a load capacitor;
- first and second pass-through logic (PTL) cells that each implement the same Boolean logic, each said PTL cell having a logical input, a bias input and first and second parallel outputs configured to switch in opposition, said logical inputs of said PTL cells coupled to the first logical input;
- an inductor coupled between the bias inputs of the first and second PTL cells;
- a first unidirectional switch coupled between the second output of the first PTL cell and the logical output at the top of the load capacitor, when enabled said first unidirectional switch allowing the inductor to pull charge from the bottom of the capacitor through the inductor to the top of the load capacitor to switch a logic level 1 at the logical output, said first unidirectional switch trapping charge on the top of the capacitor to hold the logic level 1 and prevent oscillation;
- a second unidirectional switch coupled between the first output of the second PTL cell and the bottom of the load capacitor, when enabled said second unidirectional switch allowing the inductor to pull charge from the top of the capacitor through the inductor to the bottom of the load capacitor to switch a logic level 0 at the logical output, said second unidirectional switch trapping charge on the bottom of the capacitor to hold the logic level 0 and prevent oscillation.
A low-power digital logic circuit, comprising a pair of pass-through logic (PTL) cells that are coupled between opposite sides of an inductor and a load capacitor, each said PTL cell configured to receive at least a first logical input and implement the same Boolean logic to switch first and second parallel outputs in opposition, one said output in each PTL connected directly to the load capacitor and the other said output connected through a unidirectional switch to the load capacitor, said PTL cells responsive to the first logical input to switch the unidirectional switches in opposition to allow charge to flow either in a clockwise direction to the top of the load capacitor or in a counter clockwise direction to the bottom of the load capacitor to switch a logical output at the top of the load capacitor, said unidirectional switches trapping charge on either side of the load capacitor to hold the logical output and prevent oscillation.
Dependencies are inferred from the claim text.