# US 9,438,228 B2 · High efficiency gate drive circuit for power transistors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,228 B2 - Document ID: US9438228B2 - Status: Granted - Kind: B2 - Application number: 14/384,569 - Filed: 2013-03-11 - Published: 2015-01-29 - Granted: 2016-09-06 - Earliest claimed: 2012-03-12 - Assignees: Board of Trustees of Michigan State University; Aisin Aw Co., Ltd. - Applicants: Board of Trustees of Michigan State University; Aisin Aw Co. Ltd. - Inventors: Fang Zheng Peng; Junming Zhang; Zhiqian Chen - Web page: https://patentgrep.com/patent/US9438228B2 ## CPC - H03K 17/60: the devices being bipolar transistors (bipolar transistors having four or more electrodes H03K17/72) - H03K 17/0826: {in bipolar transistor switches} - H03K 17/166: {Soft switching} - H03K 17/168: {in composite switches} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An improved gate drive circuit is provided for a power device, such as a transistor. The gate driver circuit may include: a current control circuit; a first secondary current source that is used to control the switching transient during turn off of the power transistor and a second secondary current source that is used to control the switching transient during turn on of the power transistor. In operation, the current control circuit operates, during turn on of the power transistor, to source a gate drive current to a control node of the power transistor and, during turn off of the power transistor, to sink a gate drive current from the control node of the power transistor. The first and second secondary current sources adjust the gate drive current to control the voltage or current rate of change and thereby the overshoot during the switching transient. ## Claims ### Claim 1 A gate drive circuit for a power transistor, comprising: a power transistor having a control node; a current control circuit operable, during turn on of the power transistor, to source a gate drive current to a control node of the power transistor and, during turn off of the power transistor, to sink a gate drive current from the control node of the power transistor; a first secondary current source distinct from the current control circuit and coupled directly to the control node, the first secondary current source is configured to receive a first control signal and adjust the gate drive current, during turn off of the power transistor, in accordance with the first control signal, the first control signal being indicative of a rate of change of current passing through the power transistor; and a second secondary current source distinct from the current control circuit and coupled directly to the control node, the second secondary current source is configured to receive a second control signal and adjust the gate drive current, during turn on of the power transistor, in accordance with the second control signal, the second control signal being indicative of a rate of change of current passing through the power transistor. ### Claim 2 (depends on 1) The gate drive circuit of claim 1 further comprises a first feedback control circuit configured to receive a feedback signal measured at an emitter of the power transistor and operable to generate the first control signal; and a second feedback control circuit configured to receive the feedback signal and operable to generate the second control signal. ### Claim 3 (depends on 1) The gate drive circuit of claim 1 wherein the first secondary current source is operable, during turn off of the power transistor, to adjust the gate drive current before a gate voltage of the power transistor reaches a steady state condition and is nonoperable, during turn off of the power transistor, after the gate voltage reaches a steady state condition. ### Claim 4 (depends on 1) The gate drive circuit of claim 1 wherein the second secondary current source is operable, during turn on of the power transistor, to adjust the gate drive current before the gate voltage reaches a steady state condition and is nonoperable, during turn on of the power transistor, after the gate voltage reaches a steady state condition. ### Claim 5 (depends on 1) The gate driver circuit of claim 1 wherein the power transistor is further defined as an insulated gate bipolar transistor. ### Claim 6 (depends on 1) The gate driver circuit of claim 1 wherein the current control circuit includes a current source electrically coupled via a source switch to the control node of the power transistor and a current sink electrically coupled via a sink switch to the control node of the power transistor, such that the source switch and sink switch are controlled by a gate drive signal. ### Claim 7 (depends on 1) The gate drive circuit of claim 1 wherein the first secondary current source is implemented as a current mirror and the second secondary current source is implemented as a current mirror. ### Claim 8 (depends on 1) The gate drive circuit of claim 1 further comprises a feedback control circuit wherein the feedback control circuit generates a control signal, in accordance with a reference signal, for at least one of the first secondary current source and the second secondary current source and the reference signal is adjusted according to a load connected to the power transistor. ### Claim 9 A gate drive circuit for a power transistor, comprising: a power transistor having a control node; a current control circuit operable, during turn on of the power transistor, to source a gate drive current to a control node of the power transistor and, during turn off of the power transistor, to sink a gate drive current from the control node of the power transistor; a first secondary current source distinct from the current control circuit and coupled directly to the control node, the first secondary current source is configured to receive a first control signal and adjust the gate drive current, during turn off of the power transistor, in accordance with the first control signal, the first control signal being indicative of a rate of change of voltage at a collector node of the power transistor; and a second secondary current source distinct from the current control circuit and coupled directly to the control node, the second secondary current source is configured to receive a second control signal and adjust the gate drive current, during turn on of the power transistor, in accordance with the second control signal, the second control signal being indicative of a rate of change of current passing through the power transistor. ### Claim 10 (depends on 9) The gate drive circuit of claim 9 further comprises a first feedback control circuit configured to receive a feedback signal measured at an emitter of the power transistor and operable to generate the first control signal; and a second feedback control circuit configured to receive the feedback signal and operable to generate the second control signal. ### Claim 11 (depends on 9) The gate drive circuit of claim 9 wherein the first secondary current source is operable, during turn off of the power transistor, to adjust the gate drive current before a gate voltage of the power transistor reaches a steady state condition and is nonoperable, during turn off of the power transistor, after the gate voltage reaches a steady state condition. ### Claim 12 (depends on 9) The gate drive circuit of claim 9 wherein the second secondary current source is operable, during turn on of the power transistor, to adjust the gate drive current before the gate voltage reaches a steady state condition and is nonoperable, during turn on of the power transistor, after the gate voltage reaches a steady state condition. ### Claim 13 (depends on 9) The gate driver circuit of claim 9 wherein the power transistor is further defined as an insulated gate bipolar transistor. ### Claim 14 (depends on 9) The gate driver circuit of claim 9 wherein the current control circuit includes a current source electrically coupled via a source switch to the control node of the power transistor and a current sink electrically coupled via a sink switch to the control node of the power transistor, such that the source switch and sink switch are controlled by a gate drive signal. ### Claim 15 (depends on 9) The gate drive circuit of claim 9 wherein the first secondary current source is implemented as a current mirror and the second secondary current source is implemented as a current mirror. ### Claim 16 (depends on 9) The gate drive circuit of claim 9 further comprises a feedback control circuit wherein the feedback control circuit generates a control signal, in accordance with a reference signal, for at least one of the first secondary current source and the second secondary current source and the reference signal is adjusted according to a load connected to the power transistor. ### Claim 17 A gate drive circuit for a power transistor, comprising: a power transistor having a control node; a current control circuit operable, during turn on of the power transistor, to source a gate drive current to a control node of the power transistor and, during turn off of the power transistor, to sink a gate drive current from the control node of the power transistor; a first secondary current source distinct from the current control circuit and coupled directly to the control node, the first secondary current source is operable, during turn off of the power transistor, to adjust the gate drive current before a gate voltage of the power transistor reaches a steady state condition and is nonoperable, during turn off of the power transistor, after the gate voltage reaches a steady state condition; and a second secondary current source distinct from the current control circuit and coupled directly to the control node, the second secondary current source is operable, during turn on of the power transistor, to adjust the gate drive current before the gate voltage reaches a steady state condition and is nonoperable, during turn on of the power transistor, after the gate voltage reaches a steady state condition. ### Claim 18 (depends on 17) The gate drive circuit of claim 17 wherein the first secondary current source operates to adjust the gate drive current in accordance with a rate of change of current passing through the power transistor during turn off of the power transistor; and the second secondary current source operates to adjust the gate drive current in accordance with a rate of change of current passing through the power transistor during turn on of the power transistor. ### Claim 19 (depends on 17) The gate drive circuit of claim 17 wherein the current control circuit is nonoperable, during turn off of the power transistor, after the gate voltage reaches a steady and is nonoperable, during turn on of the power transistor, after the gate voltage reaches a steady state condition state condition. ### Claim 20 (depends on 17) The gate drive circuit of claim 17 wherein the first secondary current source is nonoperable during turn on of the power transistor and second secondary current source is nonoperable during turn off of the power transistor. ### Claim 21 (depends on 17) The gate driver circuit of claim 17 wherein the power transistor is further defined as an insulated gate bipolar transistor. ### Claim 22 (depends on 17) The gate driver circuit of claim 17 wherein the current control circuit includes a current source electrically coupled via a source switch to the control node of the power transistor and a current sink electrically coupled via a sink switch to the control node of the power transistor, such that the source switch and sink switch are controlled by a gate drive signal. ### Claim 23 (depends on 17) The gate drive circuit of claim 17 wherein the first secondary current source is implemented as a current mirror and the second secondary current source is implemented as a current mirror. ### Claim 24 (depends on 17) The gate drive circuit of claim 17 wherein the first secondary current source operates to adjust the gate drive current in accordance with a rate of change of voltage at a collector node of the power transistor during turn off of the power transistor; and the second secondary current source operates to adjust the gate drive current in accordance with a rate of voltage at a collector node of the power transistor during turn on of the power transistor. ### Claim 25 (depends on 24) The gate drive circuit of claim 24 further comprises a feedback control circuit configured to receive a signal indicative of the rate of change of voltage and generate a control signal for at least one of the first secondary current source and the second secondary current source. ### Claim 26 (depends on 17) The gate drive circuit of claim 17 further comprises a feedback control circuit wherein the feedback control circuit generates a control signal, in accordance with a reference signal, for at least one of the first secondary current source and the second secondary current source and the reference signal is adjusted according to a load connected to the power transistor. ### Claim 27 A gate drive circuit for a power transistor, comprising: a power transistor having a control node; a first voltage controlled current source coupled directly to the control node and configured, during turn off of the power transistor, to sink a gate drive current from the control node of the power transistor and operable, during turn off of the power transistor, to adjust the gate drive current before a gate voltage of the power transistor reaches a steady state condition, where the first voltage controlled current source configured is nonoperable, during turn off of the power transistor, after the gate voltage reaches a steady state condition; and a second voltage controlled current source coupled directly to the control node and configured, during turn on of the power transistor, to source a gate drive current to a control node of the power transistor and operable, during turn on of the power transistor, to adjust the gate drive current before the gate voltage reaches a steady state condition, where the second voltage controller current source is nonoperable, during turn on of the power transistor, after the gate voltage reaches a steady state condition. ### Claim 28 (depends on 27) The gate drive circuit of claim 27 wherein the first voltage controlled current source operates to adjust the gate drive current in accordance with a rate of change of current passing through the power transistor during turn off of the power transistor; and the second voltage controlled current source operates to adjust the gate drive current in accordance with a rate of change of current passing through the power transistor during turn on of the power transistor. ### Claim 29 (depends on 27) The gate drive circuit of claim 27 wherein the first voltage controlled current source is nonoperable during turn on of the power transistor and second voltage controlled current source is nonoperable during turn off of the power transistor. ### Claim 30 (depends on 27) The gate driver circuit of claim 27 wherein the power transistor is further defined as an insulated gate bipolar transistor. ### Claim 31 (depends on 27) The gate driver circuit of claim 27 wherein the first voltage controlled current source operates to adjust the gate drive current in accordance with a rate of change of voltage at a collector node of the power transistor during turn off of the power transistor; and the second voltage controlled current source operates to adjust the gate drive current in accordance with a rate of voltage at a collector node of the power transistor during turn on of the power transistor. ### Claim 32 (depends on 27) The gate drive circuit of claim 27 further comprises a feedback control circuit configured to receive a signal indicative of the rate of change of voltage and generate a control signal for at least one of the first secondary current source and the second secondary current source. ### Claim 33 (depends on 27) The gate drive circuit of claim 27 further comprises a feedback control circuit wherein the feedback control circuit generates a control signal, in accordance with a reference signal, for at least one of the first secondary current source and the second secondary current source and the reference signal is adjusted according to a load connected to the power transistor. ### Claim 34 A gate drive circuit for a power transistor, comprising: a power transistor having a control node; a first voltage source coupled to the control node and operable, during turn off of the power transistor, to sink a gate drive current from the control node of the power transistor; a second voltage source coupled to the control node and operable, during turn on of the power transistor, to source a gate drive current to the control node of the power transistor; a first secondary current source coupled to the control node and operable, during turn off of the power transistor, to adjust the gate drive current before a gate voltage of the power transistor reaches a steady state condition and is nonoperable, during turn off of the power transistor, after the gate voltage reaches a steady state condition; and a second secondary current source coupled to the control node and operable, during turn on of the power transistor, to adjust the gate drive current before the gate voltage reaches a steady state condition and is nonoperable, during turn on of the power transistor, after the gate voltage reaches a steady state condition. ### Claim 35 (depends on 34) The gate drive circuit of claim 34 wherein the first secondary current source operates to adjust the gate drive current in accordance with a rate of change of current passing through the power transistor during turn off of the power transistor; and the second secondary current source operates to adjust the gate drive current in accordance with a rate of change of current passing through the power transistor during turn on of the power transistor. ### Claim 36 (depends on 34) The gate drive circuit of claim 34 wherein the first voltage source is nonoperable, during turn off of the power transistor, after the gate voltage reaches a steady and the second voltage source is nonoperable, during turn on of the power transistor, after the gate voltage reaches a steady state condition state condition. ### Claim 37 (depends on 34) The gate drive circuit of claim 34 wherein the first secondary current source is nonoperable during turn on of the power transistor and second secondary current source is nonoperable during turn off of the power transistor. ### Claim 38 (depends on 34) The gate driver circuit of claim 34 wherein the power transistor is further defined as an insulated gate bipolar transistor. ### Claim 39 (depends on 34) The gate driver circuit of claim 34 wherein the first secondary current source is implemented as a current mirror and the second secondary current source is implemented as a current mirror. ### Claim 40 (depends on 34) The gate drive circuit of claim 34 wherein the first secondary current source operates to adjust the gate drive current in accordance with a rate of change of voltage at a collector node of the power transistor during turn off of the power transistor; and the second secondary current source operates to adjust the gate drive current in accordance with a rate of voltage at a collector node of the power transistor during turn on of the power transistor. ### Claim 41 (depends on 34) The gate drive circuit of claim 34 further comprises a feedback control circuit configured to receive a signal indicative of the rate of change of voltage and generate a control signal for at least one of the first secondary current source and the second secondary current source. ### Claim 42 (depends on 34) The gate drive circuit of claim 34 further comprises a feedback control circuit wherein the feedback control circuit generates a control signal, in accordance with a reference signal, for at least one of the first secondary current source and the second secondary current source and the reference signal is adjusted according to operating conditions.