# US 9,438,227 B2 · Gate-controlled p-i-n switch with a charge trapping material in the gate dielectric and a self-depleted channel

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- Number: US 9,438,227 B2
- Document ID: US9438227B2
- Status: Granted
- Kind: B2
- Application number: 14/511,569
- Filed: 2014-10-10
- Published: 2015-06-04
- Granted: 2016-09-06
- Earliest claimed: 2013-12-02
- Assignees: The Hong Kong University of Science and Technology
- Applicants: The Hong Kong University of Science and Technology
- Inventors: Johnny Kin On Sin; Xianda Zhou
- Web page: https://patentgrep.com/patent/US9438227B2

## CPC

- H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with a low on-state voltage drop and a low turn-off energy. In an aspect, a power semiconductor device is provided that embodies a normally off trench gate-controlled p-i-n switch with a charge trapping material in the gate dielectric and a self-depleted channel.

## Claims

### Claim 1

A power semiconductor structure, comprising:
a trench lined with a gate dielectric comprising three layers, comprising an inner layer, an outer layer, and a middle layer formed between the inner layer and the outer layer;
a gate electrode formed within the trench and adjacent to the inner layer;
a lightly doped channel of a first conductivity type located next to a first side of the trench and adjacent to the outer layer, wherein the lightly doped channel is doped no more than a first defined doping level;
a lightly doped drift region of the first conductivity type located below a second side of the trench, below the channel, and adjacent to the outer layer, wherein the lightly doped drift region is doped no more than a second defined doping level;
a cathode region of the first connectivity type located above and adjacent to the channel, and adjacent to the outer layer;
a heavily doped region of a second connectivity type located above and adjacent to the cathode region and adjacent to the outer layer, wherein the heavily doped region is doped no less than a third defined doping level;
another heavily doped region of the first connectivity type located above and adjacent to the cathode region and adjacent to the heavily doped region of the second connectivity type, wherein the other heavily doped region is doped no less than a fourth defined doping level; and
a cathode electrode short connecting the other heavily doped region of the first conductivity type and the heavily doped region of the second conductivity type, wherein the cathode region is connected to the cathode electrode via the other heavily doped region of the first conductivity type.

### Claim 2 (depends on 1)

The power semiconductor structure of claim 1, wherein the middle layer of the gate dielectric comprises a charge trapping material.

### Claim 3 (depends on 2)

The power semiconductor structure of claim 2, wherein the charge trapping material comprises at least one of silicon nitride or silicon nanocrystal, and wherein negative fixed charges are created in the charge trapping material.

### Claim 4 (depends on 1)

The power semiconductor structure of claim 1, wherein an inversion layer with a zero gate bias is formed between the heavily doped region of the second connectivity type and the outer layer when the power semiconductor structure is in an off-state.

### Claim 5 (depends on 4)

The power semiconductor structure of claim 4, wherein the channel has a self-depleted state when the semiconductor structure is in the off-state based on a build-in potential generated between the cathode region and the inversion layer.

### Claim 6 (depends on 5)

The power semiconductor structure of claim 5, wherein the inversion layer is transferred to an accumulation layer and the channel charge state becomes neutral when the power semiconductor structure is in an on-state based on application of a positive voltage to the gate electrode.

### Claim 7 (depends on 1)

The power semiconductor structure of claim 1, wherein the cathode region has a higher doping concentration than the channel.

### Claim 8 (depends on 7)

The power semiconductor structure of claim 7, wherein the cathode region has a doping concentration between about 1×1016 cm−3 and about 1×1019 cm−3.

### Claim 9 (depends on 1)

The power semiconductor structure of claim 1, wherein the first and the second defined doping levels are respective upper ends of a doping concentration range between about 1×1013 cm−3 and about 1×1015 cm−3 and the third and the fourth defined doping levels are respective lower ends of another doping concentration range between about 1×1018 cm−3 and about 1×1021 cm−3.

### Claim 10 (depends on 1)

The power semiconductor structure of claim 1, wherein the outer layer of the gate dielectric comprises native silicon oxide.

### Claim 11 (depends on 1)

The power semiconductor structure of claim 1, wherein the inner layer of the gate dielectric comprises at least one of silicon oxide or aluminum oxide.

### Claim 12 (depends on 1)

The power semiconductor structure of claim 1, further comprising:
a buffer region of the first conductivity type located adjacent to and below the lightly doped drift region;
a heavily doped anode region of the second conductivity type located adjacent to and below the buffer region, wherein the heavily doped anode region is doped no less than a fifth defined doping level; and
an anode electrode located adjacent to and below the anode region.

### Claim 13 (depends on 1)

The power semiconductor structure of claim 1, further comprising:
a heavily doped anode region of the second conductivity type located adjacent to and below the drift region, wherein the heavily doped anode region is doped no less than a fifth defined doping level; and
an anode electrode adjacent to and below the anode region.

### Claim 14 (depends on 1)

The power semiconductor structure of claim 1, further comprising:
a buffer region of the first conductivity type located adjacent to and below the lightly doped drift region;
a heavily doped anode region of the second conductivity type located adjacent to and below the buffer region, wherein the heavily doped anode region comprises ion implantation at an activated dose between about 1×1012 cm−2 and 1×1014 cm−2; and
an anode electrode located adjacent to and below the anode region.

### Claim 15 (depends on 1)

The power semiconductor structure of claim 1, further comprising:
a heavily doped anode region of the second conductivity type located adjacent to and below the drift region, wherein the heavily doped anode region comprises ion implantation at an activated dose between about 1×1012 cm−2 and 1×1014 cm−2; and
an anode electrode adjacent to and below the anode region.