# US 9,438,223 B2 · Transistor based switch stack having filters for preserving AC equipotential nodes > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,223 B2 - Document ID: US9438223B2 - Status: Granted - Kind: B2 - Application number: 14/281,965 - Filed: 2014-05-20 - Published: 2015-11-26 - Granted: 2016-09-06 - Earliest claimed: 2014-05-20 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Maurice Adrianus de Jongh - Web page: https://patentgrep.com/patent/US9438223B2 ## CPC - H03K 17/161: {in field-effect transistor switches} - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 17/162: {without feedback from the output circuit to the control circuit} - H04B 1/40: Circuits - H03K 17/102: {in field-effect transistor switches} - H03K 2217/0018: Special modifications or use of the back gate voltage of a FET - H03K 2217/0054: Gating switches, e.g. pass gates - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04B: TRANSMISSION ## Abstract A device for switching a radio frequency (RF) signal includes two or more field-effect transistor (FET) unit cells in a stacked or chain topology, and gate or body node filtration circuitry that preserves RF equipotential nodes. The filtration circuitry may be capacitive or resistive-capacitive. The filtration circuitry may be included in each unit cell of the device or in a gate or body bias network that is common to all unit cells in the device. ## Claims ### Claim 1 A device for switching a radio frequency (RF) signal, comprising: a plurality of field-effect transistors (FET) unit cell circuits configured as a FET stack, each FET unit cell circuit comprising a FET; a bias network circuit coupled to the FET stack; and a body filter included in the plurality of FET unit cell circuits, the body filter having a drain-source circuit, the drain-source circuit comprising a divider circuit defining a virtual node, the body filter including a body filter capacitance between a body node of the FET and the virtual node. ### Claim 2 (depends on 1) The device of claim 1, further comprising a gate filter having a gate filter capacitance coupled to the virtual node. ### Claim 3 (depends on 2) The device of claim 2, wherein the divider circuit comprises a first capacitance in series with a second capacitance, the virtual node is defined between the first capacitance and the second capacitance, and the gate filter comprises a gate filter resistance coupled between the virtual node and a gate node of the FET. ### Claim 4 (depends on 1) The device of claim 1, wherein each FET unit cell circuit of the plurality of FET unit cell circuits comprises a first FET and a second FET, the device further comprising: a first body filter having a first body filter capacitance coupled between a body node of the first FET and a gate node of the first FET; and a second body filter having a second body filter capacitance coupled between a body node of the second FET and a gate node of the second FET. ### Claim 5 (depends on 4) The device of claim 4, further comprising a shared body filter capacitance coupled between a source node of the first FET and the body node of the first FET and coupled between a drain node of the second FET and the body node of the second FET. ### Claim 6 (depends on 1) The device of claim 1, wherein the plurality of FET unit cell circuits are formed on a silicon-on-insulator (SOI) substrate. ### Claim 7 A device for switching a radio frequency (RF) signal, comprising: a plurality of field-effect transistors (FET) unit cell circuits configured as a FET stack, each FET unit cell circuit comprising a FET; and a body bias network filter circuit coupled to a body node of each FET unit cell circuit, the body bias network filter circuit having a mid-node coupled to at least one drain-source node between a pair of successive FET unit cell circuits, the body bias network filter circuit having a body bias network filter capacitance coupled between the mid-node and the body node of each FET unit cell circuit. ### Claim 8 (depends on 7) The device of claim 7, wherein the body bias network filter circuit comprises a plurality of body bias network resistances in parallel with each other with respect to a common node of the body bias network filter circuit, each body bias network resistance corresponding to one of the plurality of FET unit cell circuits, each body bias network resistance connected between the common node and the body node of a corresponding FET unit cell circuit. ### Claim 9 (depends on 7) The device of claim 7, wherein the body bias network filter circuit comprises a plurality of body bias network resistances in series with each other, and each body bias network resistance is coupled between body nodes of a pair of successive FET unit cell circuits. ### Claim 10 (depends on 7) The device of claim 7, further comprising a gate bias network filter circuit having a plurality of gate bias network resistances in parallel with each other with respect to a common node of the gate bias network filter circuit, each gate bias network resistance corresponding to one of the plurality of FET unit cell circuits, each gate bias network resistance connected between the common node and a gate node of a corresponding FET unit cell circuit. ### Claim 11 (depends on 7) The device of claim 7, further comprising a gate bias network filter circuit having a plurality of gate bias network resistances in series with each other, and each gate bias network resistance is coupled between gate nodes of a pair of successive FET unit cell circuits. ### Claim 12 (depends on 7) The device of claim 7, wherein: the body bias network filter circuit comprises a body bias network capacitor and a plurality of body bias network resistances in parallel with each other with respect to a common node of the body bias network filter circuit, each body bias network resistance corresponding to one of the plurality of FET unit cell circuits, each body bias network resistance connected between the common node of the body bias network filter circuit and the body node of a corresponding FET unit cell circuit, the body bias network capacitor coupled between the mid-node and the common node of the body bias network filter circuit; and a gate bias network filter circuit comprises a gate bias network capacitor and a plurality of gate bias network resistances in parallel with each other with respect to a common node of the gate bias network filter circuit, each gate bias network resistance corresponding to one of the plurality of FET unit cell circuits, each gate bias network resistance connected between the common node of the gate bias network filter circuit and a gate node of a corresponding FET unit cell circuit, the gate bias network capacitor coupled between the mid-node and the common node of the gate bias network filter circuit. ### Claim 13 (depends on 7) The device of claim 7, wherein: the body bias network filter circuit comprises a body bias network capacitor and a plurality of body bias network resistances in parallel with each other with respect to a common node of the body bias network filter circuit, each body bias network resistance corresponding to one of the plurality of FET unit cell circuits, each body bias network resistance connected between the common node of the body bias network filter circuit and the body node of a corresponding FET unit cell circuit, the body bias network capacitor coupled between the mid-node and the common node of the body bias network filter circuit; and a gate bias network filter circuit comprises a gate bias network capacitor and a plurality of gate bias network resistances in series with each other, and each gate bias network resistance is coupled between the gate nodes of a pair of successive FET unit cell circuits, the gate bias network capacitor coupled between the mid-node and a common node of the gate bias network filter circuit. ### Claim 14 (depends on 7) The device of claim 7, wherein: the body bias network filter circuit comprises a body bias network capacitor and a plurality of body bias network resistances in series with each other, and each body bias network resistance is coupled between body nodes of a pair of successive FET unit cell circuits, the body bias network capacitor coupled between the mid-node and a common node of the body bias network filter circuit; and a gate bias network filter circuit comprises a gate bias network capacitor and a plurality of gate bias network resistances in parallel with each other with respect to a common node of the gate bias network filter circuit, each gate bias network resistance corresponding to one of the plurality of FET unit cell circuits, each gate bias network resistance connected between the common node and a gate node of a corresponding FET unit cell circuit, the gate bias network capacitor coupled between the mid-node and the common node of the gate bias network filter circuit. ### Claim 15 (depends on 7) The device of claim 7, wherein: the body bias network filter circuit comprises a body bias network capacitor and a plurality of body bias network resistances in series with each other, and each body bias network resistance is coupled between body nodes of a pair of successive FET unit cell circuits, the body bias network capacitor coupled between the mid-node and a common node of the body bias network filter circuit; and a gate bias network filter circuit comprises a gate bias network capacitor and a plurality of gate bias network resistances in series with each other, and each gate bias network resistance is coupled between gate nodes of a pair of successive FET unit cell circuits, the gate bias network capacitor coupled between the mid-node and a common node of the gate bias network filter circuit.