# US 9,438,219 B2 · Hybrid digital pulse width modulation (PWM) based on phases of a system clock

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- Number: US 9,438,219 B2
- Document ID: US9438219B2
- Status: Granted
- Kind: B2
- Application number: 14/350,547
- Filed: 2011-12-22
- Published: 2014-09-18
- Granted: 2016-09-06
- Earliest claimed: 2011-12-22
- Assignees: Intel Corporation
- Applicants: Harish K. Krishnamurthy; Annabelle Pratt; Mark L. Neidengard; George E. Matthew; James Alexander Darnes
- Inventors: Harish K. Krishnamurthy; Annabelle Pratt; Mark L. Neidengard; George E. Matthew; James Alexander Darnes
- Web page: https://patentgrep.com/patent/US9438219B2

## CPC

- H03K 7/08: Duration or width modulation {; Duty cycle modulation}
- H02M 3/155: using semiconductor devices only
- H02M 3/157: with digital control
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a D flip-flop under control of a selected phase of the system clock. Alternatively, a target count may be derived from the duty command, and an edge of the PWM pulse may be initiated when a count of the selected phase equals the target count. The pulse edge may be registered by a D flip-flop to a SR flip-flop under control of the selected phase. The phases of the system clock may be shared amongst multiple systems to generate multiple PWM signals. A system may include a DLL and digital logic, which may consist essentially of combinational logic and registers.

## Claims

### Claim 1

An apparatus, comprising, a first pulse width modulator and a controller to provide a first digital duty command to the first pulse width modulator, wherein the first digital duty command specifies a duty to within a fraction of a cycle of a system clock to the first pulse width modulator, and wherein the first pulse width modulator is configured to:
generate a first digital delay value based on a value of the first digital duty command and a maximum value of the first digital duty command;
assert an edge of a pulse based on most significant bits of the first digital delay value;
select a first one of multiple phases of the system clock based on least significant bits of the first digital delay value; and
re-time the edge of the pulse based on the first selected phase of the system clock to adjust a width of the pulse.

### Claim 2 (depends on 1)

The apparatus of claim 1, further including:
a second pulse width modulator configured identical to the first pulse width modulator, wherein the controller is further configured to provide a second digital duty command to the second pulse width modulator; and
a delay locked loop to provide the multiple phases of the system clock to each of the first and second pulse width modulators.

### Claim 3 (depends on 2)

The apparatus of claim 2, further including first and second voltage regulators, wherein:
the first pulse width modulator is configured to control the first voltage regulator; and
the second pulse width modulator is configured to control the second voltage regulator.

### Claim 4 (depends on 2)

The apparatus of claim 2, further including a multi-phase voltage regulator, wherein:
the first pulse width modulator is configured to control a first phase of the multi-phase voltage regulator;
the second pulse width modulator is configured to control a second phase of the multi-phase voltage regulator; and
the controller is further configured to selectively enable the first and second pulse width modulators.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first pulse width modulator includes a register to re-time the edge of the pulse based on the first selected phase of the system clock.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the register includes:
a D flip-flop to register the edge of the pulse under control of the selected phase of the system clock to re-time the edge of the pulse.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the first pulse width modulator is further configured to:
generate the first digital delay value based on a difference between one-half the maximum value of the first digital duty command and one-half the value of the first digital duty command;
assert a leading edge of the pulse based on the most significant bits of the first digital delay value; and
re-time the leading edge of the pulse based on the first selected phase of the system clock to adjust the width of the pulse.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the first pulse width modulator is further configured to:
generate a second digital delay value based on a sum of one-half the maximum value of the first digital duty command and one-half the first digital first digital duty command;
assert a trailing edge of the pulse based on most significant bits of the second digital delay value;
select a second one of the multiple phases of the system clock based on least significant bits of the second digital delay value; and
re-time the trailing edge of the pulse based on the second selected phase of the system clock to adjust the width of the pulse.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the first pulse width modulator includes:
a first D flip-flop to register the leading edge of the pulse to a SET input of a SR flip-flop under control of the first selected phase of the system clock to re-time the leading edge of the pulse; and
a second D flip-flop to register the trailing edge of the pulse to a RESET input of the SR flip-flop under control of the second select phase of the system clock to re-time the trailing edge of the pulse.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the first pulse width modulator is further configured do:
generate the first digital delay value based on a sum of one-half the maximum value of the first digital duty command and one-half the first digital first digital duty command;
assert a trailing edge of the pulse based on the most significant bits of the first digital delay value; and
re-time the trailing edge of the pulse based on the first selected phase of the system clock.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the first pulse width modulator is further configured to:
increment a count based on the first selected phase of the system clock; and
re-time the edge of the pulse when the count reaches the first digital delay value.

### Claim 12

A system, comprising, and integrated circuit device that includes:
a voltage regulator to regulate a voltage of a first voltage rail;
first circuitry to receive power from the first voltage rail; and
a first pulse width modulator to control the voltage regulator; and
a controller to provide a first digital duty command to the first pulse width modulator, wherein the first digital duty command specifies a duty to within a fraction of a cycle of a system clock to the first pulse width modulator;
wherein the first pulse width modulator is configured to,
generate a first digital delay value based on a value of the first digital duty command and a maximum value of the first digital duty command;
assert an edge of a pulse based on most significant bits of the first digital delay value;
select a first one of multiple phases of the system clock based on least significant bits of the first digital delay value; and
re-time the edge of the pulse based on the first selected phase of the system clock to adjust a width of the pulse.

### Claim 13 (depends on 12)

The system of claim 12, wherein the integrated circuit device includes a processor, further including:
a communication system to interface between the processor and a communication network;
a display to display information from the processor; and
a human interface device (HID) to provide user input to the processor.

### Claim 14 (depends on 12)

The system of claim 12, wherein the integrated circuit device further includes:
a second pulse width modulator configured identical to the first pulse width modulator, wherein the controller is further configured to provide a second digital duty command to the second pulse width modulator; and
a delay locked loop to provide the multiple phases of the system clock to each of the first and second pulse width modulators.

### Claim 15 (depends on 14)

The system of claim 14, wherein the integrated circuit device further includes:
a second voltage regulator to regulate a voltage of a second voltage rail;
second circuitry to receive power from the second voltage rail; and
wherein the second pulse width modulator is configured to control the second voltage regulator.

### Claim 16 (depends on 14)

The system of claim 14, wherein the voltage regulator includes a multi-phase voltage regulator, and wherein:
the first width modulator is configured to control a first phase of the multi-phase voltage regulator;
the second pulse width modulator is configured to control a second phase of the multi-phase voltage regulator; and
the controller is further configured to selectively enable the first and second pulse width modulators.