# US 9,438,214 B2 · DC offset cancellation circuit

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- Number: US 9,438,214 B2
- Document ID: US9438214B2
- Status: Granted
- Kind: B2
- Application number: 14/529,924
- Filed: 2014-10-31
- Published: 2015-07-02
- Granted: 2016-09-06
- Earliest claimed: 2013-12-27
- Assignees: RDC Semiconductor Co., Ltd.
- Applicants: RDC Semiconductor Co., Ltd.
- Inventors: Ming-Chou Yen
- Web page: https://patentgrep.com/patent/US9438214B2

## CPC

- H03K 5/003: Changing the DC level (reinsertion of DC component of a television signal H04N5/16)
- H03F 1/304: {and using digital means}
- H03F 2200/375: Circuitry to compensate the offset being present in an amplifier
- H03F 2203/45212: the differential amplifier being designed to have a reduced offset
- H03K 5/007: Base line stabilisation (thresholding H03K5/08)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03F: AMPLIFIERS

## Abstract

A DC offset cancellation circuit is provided. A first DC current and a first sensing current are superposed with each other to generate a first superposed current. A second DC current and a second sensing current are superposed with each other to generate a second superposed current. The first superposed current is converted into a first voltage signal. The second superposed current is converted into a second voltage signal. After the first voltage signal and the second voltage signal are received by a differential amplifier, an output signal is generated. The output signal is processed into a DC value. The DC value is converted into a DC current signal. The superposing unit generates the first DC current and the second DC current according to the DC current signal, so that the first superposed current and the second superposed current have the same DC offset.

## Claims

### Claim 1

A DC offset cancellation circuit receiving a first sensing current from a first sensing unit and a second sensing current from a second sensing unit, the DC offset cancellation circuit comprising:
a superposing unit for generating a first DC current and a second DC current, wherein after the first DC current and the first sensing current are superposed with each other by the superposing unit, a first superposed current is generated, wherein after the second DC current and the second sensing current are superposed with each other by the superposing unit, a second superposed current is generated;
a first current-to-voltage converter for converting the first superposed current into a first voltage signal;
a second current-to-voltage converter for converting the second superposed current into a second voltage signal;
a differential amplifier having a first input end receiving the first voltage signal, a second input end receiving the second voltage signal, and an output end generating an output signal;
a processing unit for receiving the output signal and processing the output signal into a DC value and a control signal, wherein a gain value of the differential amplifier is correspondingly adjusted according to the control signal; and
a current digital-to-analog converter for converting the DC value into a DC current signal and issuing the DC current signal to the superposing unit,
wherein the superposing unit generates the first DC current and the second DC current according to the DC current signal, so that the first superposed current and the second superposed current have the same DC offset.

### Claim 2 (depends on 1)

The DC offset cancellation circuit as claimed in claim 1, wherein the processing unit comprises:
an analog-to-digital converter for converting the output signal into a digitized output signal; and
a digital processing unit for processing the digitized output signal into the DC value according to a DC offset of the digitized output signal.

### Claim 3 (depends on 1)

The DC offset cancellation circuit as claimed in claim 1, wherein the DC current signal is equal to the first DC current and the second DC current is zero, so that the DC offset of the first superposed current is equal to the DC offset of the second sensing current.

### Claim 4 (depends on 1)

The DC offset cancellation circuit as claimed in claim 1, wherein the DC current signal is equal to the second DC current and the first DC current is zero, so that the DC offset of the second superposed current is equal to the DC offset of the first sensing current.

### Claim 5 (depends on 1)

The DC offset cancellation circuit as claimed in claim 1, wherein the first sensing current from the first sensing unit and the second sensing current from the second sensing unit are both photo sensing currents.