# US 9,438,212 B2 · Concurrent true and complement signal generation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,212 B2 - Document ID: US9438212B2 - Status: Granted - Kind: B2 - Application number: 13/690,130 - Filed: 2012-11-30 - Published: 2014-06-05 - Granted: 2016-09-06 - Earliest claimed: 2012-11-30 - Assignees: Avago Technologies General IP (Singapore) Pte. Ltd. - Applicants: LSI Corporation - Inventors: Manish Trivedi; Manish Umedlal Patel - Web page: https://patentgrep.com/patent/US9438212B2 ## CPC - H03K 3/356156: {with synchronous operation} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A circuit generates low-skew true and complement output signals from an input signal using an inverter, true signal generation circuitry, and complement signal generation circuitry. The inverter operates between a high-voltage reference source (VDD) and a low-voltage reference source (VSS) and inverts the input signal to generate a delayed complement input signal. The true signal generation circuitry, which comprises a p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a true output signal. The complement signal generation circuitry, which also comprises p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a complement output signal. ## Claims ### Claim 1 An apparatus comprising a true and complement signal generation circuit comprising: an inverter configured to (i) operate between a high-voltage reference source, and a low-voltage reference source, (ii) receive a true input signal, and (iii) generate a complement input signal being the complement of the true input signal; true signal generation circuitry configured to: (i) operate between the high-voltage reference source and the complement input signal and (ii) generate a true output signal; and complement signal generation circuitry configured to: (i) operate between the high-voltage reference source and the true input signal and (ii) generate a complement output signal, wherein the true signal generation circuitry and the complement signal generation circuitry are each directly coupled to both the true input signal and the complement input signal. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein skew between the true and complement output signals is less than skew between the true and complement input signals. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein: the true signal generation circuitry comprises first and second switches controlled by the true input signal; and the complement signal generation circuitry comprises a third switch controlled by the complement input signal and a fourth switch controlled by the high-voltage reference source. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein: the first and the third switches are p-type transistors; and the second and the fourth switches are n-type transistors. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein: the true signal generation circuitry comprises: a first p-type transistor coupled between the high-voltage reference source and the output signal; and a first n-type transistor coupled between the complement input signal and the output signal; and the complement signal generation circuitry comprises: a second p-type transistor coupled between the high-voltage reference source and the complement output signal; and a second n-type transistor coupled between the true input signal and the complement output signal. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the apparatus is an integrated circuit. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the true signal generation circuitry comprises at least two transistors connected in series. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the at least two transistors comprise a p-type transistor and an n-type transistor. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the complement signal generation circuitry comprises at least two transistors connected in series. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the at least two transistors comprise a p-type transistor and an n-type transistor. ### Claim 11 A method for generating true and complement output signals, the method comprising: (a) receiving a true input signal; (b) generating a complement input signal being the complement of the true input signal; (c) generating the true output signal via true signal generation circuitry configured to operate between a high-voltage reference source and the complement input signal; and (d) generating the complement output signal via complement signal generation circuitry configured to operate between the high-voltage reference source and the true input signal, wherein the true signal generation circuitry and the complement signal generation circuitry are each directly coupled to both the true input signal and the complement input signal. ### Claim 12 (depends on 11) The method of claim 11, wherein skew between the true and complement output signals is less than skew between the true and complement input signals. ### Claim 13 (depends on 11) The method of claim 11, wherein the true signal generation circuitry comprises a first transistor and second transistor connected in series and wherein the complement signal generation circuitry comprises a third transistor and fourth transistor connected in series. ### Claim 14 (depends on 13) The method of claim 13, wherein the first transistor comprises a p-type transistor and wherein the second transistor comprises an n-type transistor. ### Claim 15 (depends on 14) The method of claim 14, wherein the third transistor comprises a p-type transistor and wherein the fourth transistor comprises an n-type transistor. ### Claim 16 (depends on 11) The method of claim 11, wherein: the true signal generation circuitry comprises first and second switches controlled by the true input signal; and the complement signal generation circuitry comprises a third switch controlled by the complement input signal and a fourth switch controlled by the high-voltage reference source. ### Claim 17 An apparatus comprising a true and complement signal generation circuit comprising: an inverter configured to (i) operate between a high-voltage reference source, and a low-voltage reference source, (ii) receive a true input signal, and (iii) generate a complement input signal being the complement of the true input signal; true signal generation circuitry configured to (i) operate between (a) one of the high-voltage reference source and the low-voltage reference source and (b) the complement input signal and (ii) generate a true output signal, wherein the true signal generation circuitry comprises a first p-type transistor coupled between the high-voltage reference source and the output signal and a first n-type transistor coupled between the complement input signal and the output signal; and complement signal generation circuitry configured to (i) operate between (a) one of the high-voltage reference source and the low-voltage reference source and (b) the true input signal, and (ii) generate a complement output signal, wherein the complement signal generation circuitry comprises a second p-type transistor coupled between the high-voltage reference source and the complement output signal and a second n-type transistor coupled between the true input signal and the complement output signal, wherein: the true signal generation circuitry comprises first and second switches controlled by the true input signal; and the complement signal generation circuitry comprises a third switch controlled by the complement input signal and a fourth switch controlled by the high-voltage reference source. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein skew between the true and complement output signals is less than skew between the true and complement input signals. ### Claim 19 (depends on 17) The apparatus of claim 17, wherein the true signal generation circuitry and the complement signal generation circuitry are each directly coupled to both the true input signal and the complement input signal. ### Claim 20 (depends on 17) The apparatus of claim 17, wherein the first switch comprises a p-type transistor, wherein the second switch comprises an n-type transistor, wherein the third switch comprises a p-type transistor, and wherein the fourth switch comprises an n-type transistor.