# US 9,438,209 B2 · Implementing clock receiver with low jitter and enhanced duty cycle > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,209 B2 - Document ID: US9438209B2 - Status: Granted - Kind: B2 - Application number: 14/583,963 - Filed: 2014-12-29 - Published: 2016-06-30 - Granted: 2016-09-06 - Earliest claimed: 2014-12-29 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Andrew D. Davies; Grant P. Kesselring; Christopher W. Steffen; James D. Strom - Web page: https://patentgrep.com/patent/US9438209B2 ## CPC - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - H03K 3/353: by the use, as active elements, of field-effect transistors with internal or external positive feedback (H03K3/023, H03K3/027 take precedence) - H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) - H03L 7/10: for assuring initial synchronisation or for broadening the capture range - H03K 3/356104: {using complementary field-effect transistors (H03K3/35625 takes precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry. ## Claims ### Claim 1 A clock receiver circuit for implementing low jitter and enhanced duty cycle comprising: a differential transistor pair; an input circuit biasing a reference clock and providing biased complementary metal oxide semiconductor (CMOS) or differential clock signals to said differential transistor pair; multiple current mirrors coupled to said differential transistor pair for switching the polarity of input clock signals for enhanced signal performance, enable and inverter stages coupled between said differential transistor pair and said multiple current mirrors functioning as buffers to ensure rail to rail signaling; and cross coupled inverters coupled between said current mirrors for retaining clock signal symmetry. ### Claim 2 (depends on 1) The clock receiver circuit as recited in claim 1 wherein said input circuit enables enhanced current steering and an enhanced common mode voltage range. ### Claim 3 (depends on 1) The clock receiver circuit as recited in claim 1 includes a biasing capacitor coupled to said differential transistor pair. ### Claim 4 (depends on 3) The clock receiver circuit as recited in claim 3 wherein said biasing capacitor and said differential transistor pair function as a level translator. ### Claim 5 (depends on 1) The clock receiver circuit as recited in claim 1 wherein each said current mirror includes a series P-channel field effect transistor (PFET) and an N-channel field effect transistor (NFET) connected between voltage rails (VDD, VSS). ### Claim 6 (depends on 1) The clock receiver circuit as recited in claim 1 wherein each said cross coupled inverter includes a series connected P-channel field effect transistor (PFET) and a pair of N-channel field effect transistors (NFETs) connected between the voltage rails (VDD, and VSS). ### Claim 7 (depends on 6) The clock receiver circuit as recited in claim 6 includes a gate input to said series connected P-channel field effect transistor (PFET) and a pair of N-channel field effect transistors (NFETs) connected to a respective current mirror output node. ### Claim 8 A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a clock receiver circuit tangibly embodied in the machine readable medium used in the design process, said clock receiver circuit for implementing low jitter and enhanced duty cycle, said clock receiver circuit comprising: a differential transistor pair; a biasing capacitor coupled to said differential transistor pair; an input circuit biasing a reference clock and providing biased complementary metal oxide semiconductor (CMOS) or differential clock signals to said differential transistor pair; multiple current mirrors coupled to said differential transistor pair for switching the polarity of input clock signals for enhanced signal performance, and cross coupled inverters coupled between said current mirrors for retaining clock signal symmetry, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said clock receiver circuit. ### Claim 9 (depends on 8) The design structure of claim 8, wherein the design structure comprises a netlist, which describes said clock receiver circuit. ### Claim 10 (depends on 8) The design structure of claim 8, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits. ### Claim 11 (depends on 8) The design structure of claim 8, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications. ### Claim 12 (depends on 8) The design structure of claim 8, wherein said biasing capacitor and said differential transistor pair function as a level translator.