# US 9,438,208 B2 · Wide-band duty cycle correction circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,208 B2 - Document ID: US9438208B2 - Status: Granted - Kind: B2 - Application number: 14/299,779 - Filed: 2014-06-09 - Published: 2015-12-10 - Granted: 2016-09-06 - Earliest claimed: 2014-06-09 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Shraddha Sridhar; Vaishnav Srinivas - Web page: https://patentgrep.com/patent/US9438208B2 ## CPC - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - H03K 5/1565: {the output pulses having a constant duty cycle} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A duty cycle correction circuit includes a rising edge variable delay circuit and a falling edge variable delay circuit. The variable delay for each delay circuit depends upon an uncorrected duty cycle for an uncorrected clock signal being corrected by the duty cycle correction circuit into a corrected clock signal having a desired duty cycle. ## Claims ### Claim 1 A duty cycle correction circuit, comprising: a falling edge variable delay circuit for delaying a rising edge of an uncorrected clock signal into a first delayed signal; a first inverter for inverting the first delayed signal into an inverted first delayed signal; a rising edge variable delay circuit for delaying a falling edge of the uncorrected clock signal into a second delayed signal; a second inverter for inverting the second delayed signal into an inverted second delayed signal; and a pulse generator configured to pulse an output node voltage to a power supply voltage responsive to the first delayed signal and the first inverted delayed signal, the pulse generator being further configured to pulse the output node voltage to ground responsive to the second delayed signal and the second inverted delayed signal, wherein the pulse generator includes a first pair of switches, a second pair of switches, a third pair of switches, and a fourth pair of switches, and wherein the first pair of switches are serially connected between an output node carrying the output node voltage and a power supply node, the second pair of switches are serially connected between the output node and ground, the third pair of switches are coupled between the output node and the power supply node, and the fourth pair of switches are coupled between the output node and ground. ### Claim 2 (depends on 1) The duty cycle correction circuit of claim 1, further comprising a latch configured to latch the pulsed output node voltage. ### Claim 3 (depends on 2) The duty cycle correction circuit of claim 2, further comprising a third inverter for inverting the latched pulsed output node voltage to form a corrected clock signal. ### Claim 4 (depends on 1) The duty cycle correction circuit of claim 1, wherein the first pair of switches comprises a first PMOS transistor having a gate coupled to a node carrying the first delayed signal and a second PMOS transistor having a gate coupled to a node carrying the inverted first delayed signal. ### Claim 5 (depends on 1) The duty cycle correction circuit of claim 1, wherein the second pair of switches comprises a first NMOS transistor having a gate coupled to a node carrying the second delayed signal and a second NMOS transistor having a gate coupled to a node carrying the inverted second delayed signal. ### Claim 6 (depends on 1) The duty cycle correction circuit of claim 1, further comprising a cross-coupled pair of inverters, wherein the cross-coupled inverters are cross-coupled through switches in the first pair of switches, the second pair of switches, the third pair of switches, and the fourth pair of switches. ### Claim 7 (depends on 1) The duty cycle correction circuit of claim 1, further comprising a cross-coupled pair of inverters wherein one of the cross-coupled inverters is configured to invert the output node voltage. ### Claim 8 (depends on 7) The duty cycle correction circuit of claim 7, wherein the third set of switches is coupled between the power supply node and a PMOS transistor for a remaining one of the cross-coupled inverters. ### Claim 9 (depends on 7) The duty cycle correction circuit of claim 7, wherein the fourth set of switches is coupled between ground and an NMOS transistor for a remaining one of the cross-coupled inverters. ### Claim 10 (depends on 1) The duty cycle correction circuit of claim 1, further comprising a third inverter configured to invert a control signal into an inverted control signal, and wherein the first inverter comprises a first logic gate configured to process the first delayed signal and the inverted control signal to form the inverted first delayed signal, and wherein the second inverter comprises a second logic gate configured to process the second delayed signal and the control signal to form the inverted second delayed signal. ### Claim 11 (depends on 10) The duty cycle correction circuit of claim 10, wherein the first logic gate comprises a NOR gate and wherein the second logic gate comprises a NAND gate. ### Claim 12 A method, comprising: responsive to determining that a duty cycle for an uncorrected clock signal is greater than a desired duty cycle, delaying a falling edge of the uncorrected clock signal through a falling edge variable delay circuit to produce a first delayed signal while passing the uncorrected clock signal through a rising edge variable delay circuit with no delay to produce a second delayed signal; responsive to determining that the duty cycle for the uncorrected clock signal is less than the desired duty cycle, delaying a rising edge of the uncorrected clock signal through the rising edge variable delay circuit to produce the second delayed signal while passing the uncorrected clock signal through the falling edge variable delay circuit with no delay to produce the first delayed signal; pulsing an output node voltage to a power supply voltage responsive to the first delayed signal and pulsing the output node voltage to ground responsive to the second delayed signal; producing a corrected clock signal having the desired duty cycle from the pulsed output node voltage; and inverting the first delayed signal to form an inverted first delayed signal, wherein pulsing the output node voltage to the power supply voltage comprises pulsing the output node voltage to the power supply voltage when the first delayed signal and the inverted first delayed signal are both grounded, wherein inverting the first delayed signal comprises processing the first delayed signal with a control signal in a logic gate. ### Claim 13 (depends on 12) The method of claim 12, further comprising inverting the second delayed signal to form an inverted second delayed signal, wherein pulsing the output node voltage to ground comprises grounding the output node voltage when the second delayed signal and the inverted second delayed signal are both charged to the power supply voltage. ### Claim 14 (depends on 13) The method of claim 13, wherein inverting the second delayed signal comprises processing the second delayed signal with a control signal in a logic gate. ### Claim 15 (depends on 12) The method of claim 12, further comprising latching the pulsed output node voltage. ### Claim 16 (depends on 15) The method of claim 15, wherein producing the corrected clock signal comprises inverting the latched pulsed output node voltage to produce the corrected clock signal. ### Claim 17 A duty cycle correction circuit, comprising: means for variably delaying a rising edge of an uncorrected clock signal into a first delayed signal and for variably delaying a falling edge of the uncorrected clock signal into a second delayed signal; a pulse generator configured to pulse an output node voltage to a power supply voltage responsive to the first delayed signal, the pulse generator being further configured to pulse the output node voltage to ground responsive to the second delayed signal; a first inverter configured to invert the output node voltage into a corrected clock signal; and a second inverter configured to invert the first delayed signal into an inverted first delayed signal, wherein the pulse generator is further configured to pulse the output node voltage to the power supply voltage when both the first delayed signal and the inverted first delayed signal are grounded, wherein the second inverter comprises a NOR gate. ### Claim 18 (depends on 17) The duty cycle correction circuit of claim 17, further comprising: a third inverter configured to invert the second delayed signal into an inverted second delayed signal, wherein the pulse generator is further configured to pulse the output node voltage to ground when both the second delayed signal and the inverted second delayed signal are charged to the power supply voltage. ### Claim 19 (depends on 18) The duty cycle correction circuit of claim 18, wherein the third inverter comprises a NAND gate. ### Claim 20 (depends on 18) The duty cycle correction circuit of claim 18, wherein the pulse generator comprises a first pair of switches and a second pair of switches. ### Claim 21 (depends on 20) The duty cycle correction circuit of claim 20, wherein the first pair of switches are serially connected between an output node carrying the output node voltage and a power supply node, and wherein the second pair of switches are serially connected between the output node and ground.