# US 9,438,207 B2 · Semiconductor device, electronic component, and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,207 B2 - Document ID: US9438207B2 - Status: Granted - Kind: B2 - Application number: 14/882,816 - Filed: 2015-10-14 - Published: 2016-04-21 - Granted: 2016-09-06 - Earliest claimed: 2014-10-17 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Yoshiyuki Kurokawa - Web page: https://patentgrep.com/patent/US9438207B2 ## CPC - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 3/037: Bistable circuits - H03K 3/356: Bistable circuits - H03K 3/86: Generating pulses by means of delay lines and not covered by the preceding subgroups - H03K 5/134: with field-effect transistors - H03K 19/09441: {of the same canal type} - H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/1776: for memories - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - H03K 2005/00195: {using FET's} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal. ## Claims ### Claim 1 A semiconductor device comprising a logic circuit capable of storing configuration data, wherein the logic circuit comprises latch circuits, an arithmetic circuit, a delay circuit, and an output timing generation circuit, wherein each of the latch circuits is capable of receiving a pulse signal from an adjacent logic circuit and outputting a first signal and a second signal, wherein a third signal obtained by a logical operation on the first signals controls power supply to the arithmetic circuit and the delay circuit, wherein the arithmetic circuit is capable of receiving the second signals and outputting a fourth signal, wherein the second signal is obtained by delaying the first signal in each of the latch circuits, wherein the delay circuit is capable of receiving the third signal and outputting a fifth signal, wherein the fifth signal is obtained by delaying the third signal so as to correspond to a delay in a critical path of the arithmetic circuit, and wherein the output timing generation circuit is capable of receiving a sixth signal obtained by a logical operation on the third signal and the fifth signal and resetting the latch circuits. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the logic circuit comprises a register and an output signal generation circuit, wherein the output timing generation circuit is capable of outputting a seventh signal, an eighth signal, and a ninth signal, wherein the register is capable of receiving the fourth signal from the logic circuit and outputting the fourth signal to the output signal generation circuit according to the seventh signal, and wherein the output signal generation circuit is capable of outputting the fourth signal to an adjacent logic circuit according to the eighth signal and the ninth signal. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the arithmetic circuit is capable of switching functions in accordance with the configuration data. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the configuration data is stored in a memory circuit comprising a transistor containing an oxide semiconductor in a channel formation region. ### Claim 5 (depends on 1) An electronic component comprising: the semiconductor device according to claim 1; and a lead. ### Claim 6 (depends on 5) An electronic device comprising: the electronic component according to claim 5; and a display portion, a speaker, a microphone, or an operation button. ### Claim 7 A semiconductor device comprising a logic circuit capable of storing configuration data, wherein the logic circuit comprises latch circuits, multiplexers, an arithmetic circuit, a delay circuit, and an output timing generation circuit, wherein each of the latch circuits is capable of receiving a pulse signal from an adjacent logic circuit and outputting a first signal and a second signal, wherein a third signal obtained by a logical operation on the first signals controls power supply to the arithmetic circuit and the delay circuit, wherein each of the multiplexers is capable of receiving each of the second signals and a binary data signal from an adjacent logic circuit and outputting the second signal or the binary data signal to the arithmetic circuit, wherein the second signal is obtained by delaying the first signal in each of the latch circuits, wherein the arithmetic circuit is capable of receiving the second signal or the binary data signal and outputting a fourth signal, wherein the delay circuit is capable of receiving the third signal and outputting a fifth signal, wherein the fifth signal is obtained by delaying the third signal so as to correspond to a delay in a critical path of the arithmetic circuit, and wherein the output timing generation circuit is capable of receiving a sixth signal obtained by a logical operation on the third signal and the fifth signal and resetting the latch circuits. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the logic circuit comprises a register and an output signal generation circuit, wherein the output timing generation circuit is capable of outputting a seventh signal, an eighth signal, and a ninth signal, wherein the register is capable of receiving the fourth signal from the logic circuit and outputting the fourth signal to the output signal generation circuit according to the seventh signal, and wherein the output signal generation circuit is capable of outputting the fourth signal to an adjacent logic circuit according to the eighth signal and the ninth signal. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein the arithmetic circuit is capable of switching functions in accordance with the configuration data. ### Claim 10 (depends on 7) The semiconductor device according to claim 7, wherein the configuration data is stored in a memory circuit comprising a transistor containing an oxide semiconductor in a channel formation region. ### Claim 11 (depends on 7) An electronic component comprising: the semiconductor device according to claim 7; and a lead. ### Claim 12 (depends on 11) An electronic device comprising: the electronic component according to claim 11; and a display portion, a speaker, a microphone, or an operation button.