# US 9,438,206 B2 · Storage circuit and semiconductor device

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- Number: US 9,438,206 B2
- Document ID: US9438206B2
- Status: Granted
- Kind: B2
- Application number: 14/471,322
- Filed: 2014-08-28
- Published: 2015-03-05
- Granted: 2016-09-06
- Earliest claimed: 2013-08-30
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Yukio Maehashi; Seiichi Yoneda; Wataru Uesugi
- Web page: https://patentgrep.com/patent/US9438206B2

## CPC

- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- H03K 3/356: Bistable circuits
- H03K 3/356104: {using complementary field-effect transistors (H03K3/35625 takes precedence)}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

## Claims

### Claim 1

A storage circuit comprising:
a first logic circuit;
a second logic circuit;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a first capacitor;
a second capacitor;
a first node;
a second node; and
a third node,
wherein the first capacitor is connected to the first node,
wherein an input terminal of the second logic circuit is connected to the second node,
wherein the first transistor is configured to control connection between an output terminal of the first logic circuit and the first node,
wherein a first clock signal is input to a gate of the first transistor,
wherein the second transistor is configured to control connection between the first node and the second node,
wherein a second clock signal is input to a gate of the second transistor,
wherein the second capacitor is connected to the third node,
wherein the third transistor is configured to control connection between the input terminal of the second logic circuit and the third node,
wherein the fourth transistor is configured to control connection between the first node and the third node,
wherein phases of the first clock signal and the second clock signal are inverted from each other, and
wherein a channel formation region of each of the first transistor, the second transistor, the third transistor and the fourth transistor includes an oxide semiconductor.

### Claim 2 (depends on 1)

The storage circuit according to claim 1, wherein each of the first logic circuit and the second logic circuit is an inverter.

### Claim 3 (depends on 1)

A semiconductor device comprising the storage circuit according to claim 1.

### Claim 4

A storage circuit comprising:
a first logic circuit;
a second logic circuit;
a first inverter;
a second inverter;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a first capacitor;
a second capacitor;
a first node;
a second node;
a third node; and
a fourth node,
wherein the first capacitor is connected to the first node,
wherein an input terminal of the second logic circuit is connected to the fourth node,
wherein the first inverter and the second inverter are connected to each other in series between the second node and the fourth node,
wherein the first transistor is configured to control connection between an output terminal of the first logic circuit and the first node,
wherein a first clock signal is input to a gate of the first transistor,
wherein the second transistor is configured to control connection between the first node and the second node,
wherein a second clock signal is input to a gate of the second transistor,
wherein the second capacitor is connected to the third node,
wherein the third transistor is configured to control connection between the fourth node and the third node,
wherein the fourth transistor is configured to control connection between the first and the third node,
wherein phases of the first clock signal and the second clock signal are inverted from each other, and
wherein a channel formation region of each of the first transistor, the second transistor, the third transistor and the fourth transistor includes an oxide semiconductor.

### Claim 5 (depends on 4)

The storage circuit according to claim 4, further comprising a switch configured to connect an input terminal of the first inverter to an output terminal of the second inverter,
wherein while supply of the first clock signal and the second clock signal is stopped, the switch is turned on.

### Claim 6 (depends on 5)

The storage circuit according to claim 5,
wherein the switch is a fifth transistor, and
wherein a channel formation region of the fifth transistor includes an oxide semiconductor.

### Claim 7 (depends on 4)

The storage circuit according to claim 4, wherein each of the first logic circuit and the second logic circuit is an inverter.

### Claim 8 (depends on 4)

A semiconductor device comprising the storage circuit according to claim 4.

### Claim 9

A semiconductor device comprising:
a first inverter;
a second inverter;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a first capacitor; and
a second capacitor,
wherein an output terminal of the first inverter is connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the second transistor is connected to an input terminal of the second inverter,
wherein one of a source and a drain of the third transistor is connected to the input terminal of the second inverter,
wherein the other of the source and the drain of the third transistor is connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is connected to the one of the source and the drain of the second transistor,
wherein the first capacitor is connected to the other of the source and the drain of the first transistor,
wherein the second capacitor is connected to the other of the source and the drain of the third transistor, and
wherein a channel formation region of each of the first transistor, the second transistor, the third transistor and the fourth transistor includes an oxide semiconductor.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, further comprising a third inverter and a fourth inverter and a switch,
wherein an input terminal of the third inverter is connected to the other of the source and the drain of the second transistor,
wherein an output terminal of the third inverter is connected to an input terminal of the fourth inverter,
wherein an output terminal of the fourth inverter is connected to the input terminal of the second inverter,
wherein a first terminal of the switch is connected to the input terminal of the third inverter, and
wherein a second terminal of the switch is connected to the output terminal of the fourth inverter.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10
wherein the switch is a fifth transistor, and
wherein a channel formation region of the fifth transistor includes an oxide semiconductor.