# US 9,438,182 B2 · Digital class-D amplifier and digital signal processing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,182 B2 - Document ID: US9438182B2 - Status: Granted - Kind: B2 - Application number: 14/358,182 - Filed: 2012-10-30 - Published: 2014-11-27 - Granted: 2016-09-06 - Earliest claimed: 2011-11-17 - Assignees: ST-Ericsson SA - Applicants: ST-Ericsson SA - Inventors: Carlo Crippa; Rossella Bassoli - Web page: https://patentgrep.com/patent/US9438182B2 ## CPC - H03F 3/185: with field-effect devices (H03F3/187 takes precedence) - H03F 3/187: in integrated circuits - H03F 3/2175: {using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence)} - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03K 7/08: Duration or width modulation {; Duty cycle modulation} - H03F 2200/165: A filter circuit coupled to the input of an amplifier - H03F 2200/351: Pulse width modulation being used in an amplifying circuit - H03F 2200/78: A comparator being used in a controlling circuit of an amplifier - H03F 2203/21112: A filter circuit being added at the input of a power amplifier stage - H03F 2203/21196: the supply voltage of a power amplifier being switchable controlled - H03F: AMPLIFIERS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]). The PWM conversion module (PW_CM) comprises: a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), the first reference triangular waveform having a frequency (f_osc) much lower than said clock frequency (f.s); a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing a differential output pulse width modulated signal (yn[n],yp[n]). ## Claims ### Claim 1 A digital class D amplifier comprising a pulse width modulator (PWM) comprising: a digital loop filter having a first input configured to receive an input signal and a second input configured to receive a feedback signal, the digital loop filter configured to process, at a clock frequency, the input and feedback signals to output a filtered digital signal; and a PWM conversion module having an input for receiving the filtered digital signal and having a first output connected to the second input of the digital loop filter, the PWM conversion module configured to process the filtered digital signal and provide at the first output the feedback signal, said PWM conversion module comprising: a first comparator configured to compare the filtered digital signal with a first reference triangular waveform to provide a first PWM signal, the first reference triangular waveform having a frequency substantially lower than the clock frequency; a second comparator configured to compare the filtered digital signal with a second reference triangular waveform to provide a second PWM signal, the second reference triangular waveform being the inverse of the first triangular waveform, and the first and second PWM signals representing in their combination a differential output pulse width modulated signal; and an algebraic adder having a first input coupled to an output of the first comparator and a second input coupled to an output of the second comparator, the algebraic adder configured to combine the first and said second PWM signals to provide the feedback signal. ### Claim 2 (depends on 1) The digital class D amplifier according to claim 1, further comprising one of a differential switching driver and a digital buffer, wherein the one of the differential switching driver and the digital buffer includes a first input for receiving the first PWM signal and a second input for receiving the second PWM signal. ### Claim 3 (depends on 1) The digital class D amplifier according to claim 1, wherein the digital loop filter comprises a cascade of integrators with feedback (CIFB) filter. ### Claim 4 (depends on 3) The digital class D amplifier according to claim 3, wherein the CIFB filter comprises a 4th order filter. ### Claim 5 (depends on 1) The digital class D amplifier according to claim 1, wherein the digital loop filter comprises a cascade of integrators with feedforward (CIFF) filter. ### Claim 6 (depends on 1) The digital class D amplifier according to claim 1, wherein the algebraic adder provides the feedback signal as the digital difference between the first and second PWM signals. ### Claim 7 (depends on 6) The digital class D amplifier according to claim 6, wherein the feedback signal can selectively have the following values: “1”, “0” and “−1”. ### Claim 8 (depends on 7) The digital class D amplifier according to claim 7, wherein the first and second PWM signals represent a quaternary PWM modulation of the filtered digital signal. ### Claim 9 A mobile phone platform comprising a digital class D amplifier comprising a pulse width modulator (PWM), the digital class D amplifier comprising: a digital loop filter having a first input configured to receive an input signal and a second input configured to receive a feedback signal, the digital loop filter configured to process, at a clock frequency, the input and feedback signals to output a filtered digital signal; and a PWM conversion module having an input for receiving the filtered digital signal and having a first output connected to the second input of the digital loop filter, the PWM conversion module configured to process the filtered digital signal and provide at the first output the feedback signal, said PWM conversion module comprising: a first comparator configured to compare the filtered digital signal with a first reference triangular waveform to provide a first PWM signal, the first reference triangular waveform having a frequency substantially lower than the clock frequency; a second comparator configured to compare the filtered digital signal with a second reference triangular waveform to provide a second PWM signal, the second reference triangular waveform being the inverse of the first triangular waveform, and the first and second PWM signals representing in their combination a differential output pulse width modulated signal; and an algebraic adder having a first input coupled to an output of the first comparator and a second input coupled to an output of the second comparator, the algebraic adder configured to combine the first and said second PWM signals to provide the feedback signal. ### Claim 10 A digital signal processing method for processing an input digital signal and obtaining an output pulse width modulated (PWM) signal, the method comprising: digital loop filtering, at clock frequency, the input digital signal and a feedback signal to provide a filtered digital signal; processing the filtered digital signal to provide the feedback signal; wherein processing the filtered digital signal comprises: comparing the filtered digital signal with a first reference triangular waveform, in a first comparator, to provide a first PWM signal, the first reference triangular waveform having a frequency substantially lower than the clock frequency; comparing the filtered digital signal with a second reference triangular waveform, in a second comparator, to provide a second PWM signal, the second reference triangular waveform being the inverse of the first triangular waveform; algebraically combining the first PWM signal and the second PWM signal to obtain the feedback signal in an algebraic adder, said algebraic adder having a first input coupled to an output of the first comparator and a second input coupled to an output of the second comparator; wherein the output pulse width modulated signal comprises a differential signal comprising the first and second PWM signals. ### Claim 11 (depends on 10) The digital signal processing method according to claim 10, further comprising driving a load with the differential signal comprising the first and second PWM signals. ### Claim 12 (depends on 1) The digital class D amplifier according to claim 1, wherein the algebraic adder is configured to algebraically add the first and the second PWM signals, and wherein the algebraically added first and second PWM signals generates the feedback signal.