# US 9,438,176 B2 · Low noise amplifier

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- Number: US 9,438,176 B2
- Document ID: US9438176B2
- Status: Granted
- Kind: B2
- Application number: 14/256,191
- Filed: 2014-04-18
- Published: 2014-10-23
- Granted: 2016-09-06
- Earliest claimed: 2013-04-19
- Assignees: Industry-Academic Cooperation Foundation, Yonsei University
- Applicants: Industry-Academic Cooperation Foundation, Yonsei University
- Inventors: Junyoung Jang; Honggul Han; Tae Wook Kim
- Web page: https://patentgrep.com/patent/US9438176B2

## CPC

- H03F 1/26: Modifications of amplifiers to reduce influence of noise generated by amplifying elements
- H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H03F 1/32: Modifications of amplifiers to reduce non-linear distortion (by negative feedback H03F1/34)
- H03F 2200/294: the amplifier being a low noise amplifier [LNA]
- H03F 2203/45306: the common gate stage implemented as dif amp eventually for cascode dif amp
- H03F 2203/45318: the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled
- H03F: AMPLIFIERS

## Abstract

Provided is a low noise amplifier. The low noise amplifier includes an input transistor receiving and amplifying a signal, an output transistor amplifying the signal amplified by the input transistor, and an inverting unit inverting the signal which is amplified by the input transistor and applying the inverted signal to a gate of the output transistor.

## Claims

### Claim 1

A low noise amplifier comprising:
an input transistor receiving and amplifying a signal;
an output transistor amplifying the signal amplified by the input transistor; and
an inverting unit inverting the signal which is amplified by the input transistor, and applying the inverted signal to a gate of the output transistor,
wherein the input transistor comprises first and second transistors which receive and amplify a differential input signal,
the output transistor comprises third and fourth transistors which amplify signals amplified by the first and second transistors, and
the inverting unit comprises an output cross-coupling unit connecting the third transistor to the fourth transistor in a cross-coupled configuration,
wherein the output cross-coupling unit is configured such that an output terminal of the first transistor is connected to a gate of the fourth transistor through a capacitor, and an output terminal of the second transistor is connected to a gate of the third transistor through a capacitor.

### Claim 2 (depends on 1)

The low noise amplifier of claim 1, wherein the input transistor and the output transistor are connected to each other in a cascode configuration.

### Claim 3 (depends on 2)

The low noise amplifier of claim 2, wherein the input transistor and the output transistor are connected to each other in a folded cascode configuration.

### Claim 4

A low noise amplifier comprising:
an input transistor receiving and amplifying a signal;
an output transistor amplifying the signal amplified by the input transistor;
an inverting unit inverting the signal which is amplified by the input transistor, and applying the inverted signal to a gate of the output transistor; and
an input cross-coupling unit,
wherein the input transistor comprises first and second transistors which receive and amplify a differential input signal,
the output transistor comprises third and fourth transistors which amplify signals amplified by the first and second transistors, and
the input cross-coupling unit connects the first transistor and the second transistor to each other in a cross-coupled configuration.

### Claim 5 (depends on 4)

The low noise amplifier of claim 4, wherein the input cross-coupling unit applies the signal, which is input to the first transistor, to a gate of the second transistor, and applies the signal, which is input to the second transistor, to a gate of the first transistor.

### Claim 6 (depends on 4)

The low noise amplifier of claim 4, wherein the input cross-coupling unit is configured such that an input terminal of the first transistor is connected to a gate of the second transistor through a capacitor, and an input terminal of the second transistor is connected to a gate of the first transistor through a capacitor.