# US 9,438,105 B2 · Silicon-on-insulator-based voltage generation circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,105 B2 - Document ID: US9438105B2 - Status: Granted - Kind: B2 - Application number: 14/747,711 - Filed: 2015-06-23 - Published: 2015-10-15 - Granted: 2016-09-06 - Earliest claimed: 2012-07-23 - Assignees: Smarter Microelectronics (Guang Zhou) Co., Ltd. - Applicants: Smarter Microelectronics (Guang Zhou) Co., Ltd. - Inventors: Yang Li; Yaohui Guo; Jian Sun - Web page: https://patentgrep.com/patent/US9438105B2 ## CPC - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - G05F 3/205: {Substrate bias-voltage generators (for static stores G11C5/146)} - H02M 3/071: {adapted to generate a negative voltage output from a positive voltage source} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A silicon-on-insulator (SOI) based positive/negative voltage generation circuit includes: an inverter including an NMOS transistor and a PMOS transistor, a first transfer capacitor coupled to the PMOS transistor, a first output capacitor, a second transfer capacitor coupled to the NMOS transistor, a second output capacitor, a first diode disposed between the first transfer capacitor and the first output capacitor, a second diode disposed between the second transfer capacitor and the second output capacitor, one end of the first output capacitor is coupled to the ground, one end of the second output capacitor is coupled to the ground; wherein an output voltage of the inverter is controlled by a single-phase clock to flip periodically, charge the first transfer capacitor through a parasitic diode of the PMOS transistor, and charge the second transfer capacitor through a parasitic diode of the NMOS transistor. ## Claims ### Claim 1 A silicon-on-insulator (SOI) based positive/negative voltage generation circuit, comprising: an inverter comprising an NMOS transistor and a PMOS transistor, a first transfer capacitor coupled to the PMOS transistor, a first output capacitor, a second transfer capacitor coupled to the NMOS transistor, a second output capacitor, a first diode disposed between the first transfer capacitor and the first output capacitor, a second diode disposed between the second transfer capacitor and the second output capacitor, one end of the first output capacitor is coupled to the ground, one end of the second output capacitor is coupled to the ground; wherein an output voltage of the inverter is controlled by a single-phase clock to flip periodically, charge the first transfer capacitor through a parasitic diode of the PMOS transistor, and charge the second transfer capacitor through a parasitic diode of the NMOS transistor; in a sub-circuit that generates a positive voltage, a unidirectional current flows from the first transfer capacitor through the first diode to the first output capacitor, thereby generating a positive output voltage; in a sub-circuit that generates a negative voltage, a unidirectional current flows from the second output capacitor through the second diode to the second transfer capacitor, thereby generating a negative output voltage. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the first diode comprises one or more diodes. ### Claim 3 (depends on 2) The circuit of claim 2, wherein if the first diode is a single diode, a positive electrode of the first diode is coupled to a substrate of the PMOS transistor, a negative electrode of the first diode is coupled to another end of the first output capacitor, wherein the other end of the first output capacitor is a positive voltage output end. ### Claim 4 (depends on 2) The circuit of claim 2, wherein if the first diode comprises a plurality of diodes, the plurality of the first diodes are connected in series, a positive electrode of the first diode in the plurality of the first diodes that is connected to the PMOS transistor is connected to a substrate of the PMOS transistor, a negative electrode of the first diode in the plurality of the first diodes that is connected to the first output capacitor is connected to another end of the first output capacitor, the other end of the first output capacitor is a positive voltage output end. ### Claim 5 (depends on 1) The circuit of claim 1, wherein the second diodes comprises one or more diodes. ### Claim 6 (depends on 5) The circuit of claim 5, wherein if the second diode comprises a single diode, a positive electrode of the second diode is coupled to another end of the second output capacitor, a negative electrode of the second diode is coupled to a substrate of the NMOS transistor; the other end of the second output capacitor is a negative voltage output end. ### Claim 7 (depends on 5) The circuit of claim 5, wherein if the second diode comprises a plurality of diodes, the plurality of second diodes are connected in series, a positive electrode of the second diode in the plurality of second diodes that is connected to the second output capacitor is connected to another end of the second output capacitor, a negative electrode of the second diode in the plurality of second diodes that is connected to the NMOS transistor is connected to a substrate of the NMOS transistor; the other end of the second output capacitor is a negative voltage output end. ### Claim 8 (depends on 1) The circuit of claim 1, wherein a first transfer capacitor is connected between a substrate and a drain electrode of the PMOS transistor; a second transfer capacitor is connected between a substrate and a drain electrode of the NMOS transistor. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the input end of the inverter is connected to the output end of the single-phase clock. ### Claim 10 (depends on 1) The circuit of claim 1, wherein the positive output voltage generated is higher than a power supply voltage; the negative output voltage generated is lower than a ground electrical level. ### Claim 11 (depends on 1) The circuit of claim 1, wherein, the substrate used in SOI process is high-resistivity silicon, or low-resistivity silicon, or silicon on complete insulator substrate. ### Claim 12 An integrated circuit comprising a silicon-on-insulator (SOI) based positive/negative voltage generation circuit, the SOI-based positive/negative voltage generation circuit comprising: an inverter comprising an NMOS transistor and a PMOS transistor, a first transfer capacitor coupled to the PMOS transistor, a first output capacitor, a second transfer capacitor coupled to the NMOS transistor, a second output capacitor, a first diode disposed between the first transfer capacitor and the first output capacitor, a second diode disposed between the second transfer capacitor and the second output capacitor, one end of the first output capacitor is coupled to the ground, one end of the second output capacitor is coupled to the ground; wherein an output voltage of the inverter is controlled by a single-phase clock to flip periodically, charge the first transfer capacitor through a parasitic diode of the PMOS transistor, and charge the second transfer capacitor through a parasitic diode of the NMOS transistor; in a sub-circuit that generates a positive voltage, a unidirectional current flows from the first transfer capacitor through the first diode to the first output capacitor, thereby generating a positive output voltage; in a sub-circuit that generates a negative voltage, a unidirectional current flows from the second output capacitor through the second diode to the second transfer capacitor, thereby generating a negative output voltage. ### Claim 13 (depends on 12) The integrated circuit of claim 12, wherein the first diode comprises one or more diodes. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein if the first diode is a single diode, a positive electrode of the first diode is coupled to a substrate of the PMOS transistor, a negative electrode of the first diode is coupled to another end of the first output capacitor, wherein the other end of the first output capacitor is a positive voltage output end. ### Claim 15 (depends on 13) The integrated circuit of claim 13, wherein if the first diode comprises a plurality of diodes, the plurality of the first diodes are connected in series, a positive electrode of the first diode in the plurality of the first diodes that is connected to the PMOS transistor is connected to a substrate of the PMOS transistor, a negative electrode of the first diode in the plurality of the first diodes that is connected to the first output capacitor is connected to another end of the first output capacitor, the other end of the first output capacitor is a positive voltage output end. ### Claim 16 (depends on 12) The integrated circuit of claim 12, wherein if the second diode comprises a single diode, a positive electrode of the second diode is coupled to another end of the second output capacitor, a negative electrode of the second diode is coupled to a substrate of the NMOS transistor; the other end of the second output capacitor is a negative voltage output end. ### Claim 17 (depends on 12) The integrated circuit of claim 12, wherein if the second diode comprises a plurality of diodes, the plurality of second diodes are connected in series, a positive electrode of the second diode in the plurality of second diodes that is connected to the second output capacitor is connected to another end of the second output capacitor, a negative electrode of the second diode in the plurality of second diodes that is connected to the NMOS transistor is connected to a substrate of the NMOS transistor; the other end of the second output capacitor is a negative voltage output end. ### Claim 18 (depends on 12) The integrated circuit of claim 12, wherein a first transfer capacitor is connected between a substrate and a drain electrode of the PMOS transistor; a second transfer capacitor is connected between a substrate and a drain electrode of the NMOS transistor. ### Claim 19 (depends on 12) The integrated circuit of claim 12, wherein the input end of the inverter is connected to the output end of the single-phase clock. ### Claim 20 (depends on 12) The integrated circuit of claim 12, wherein the positive output voltage generated is higher than a power supply voltage; the negative output voltage generated is lower than a ground electrical level.