# US 9,437,816 B2 · Phase change memory structures and methods

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- Number: US 9,437,816 B2
- Document ID: US9437816B2
- Status: Granted
- Kind: B2
- Application number: 14/812,284
- Filed: 2015-07-29
- Published: 2015-12-03
- Granted: 2016-09-06
- Earliest claimed: 2010-08-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Sanh D. Tang
- Web page: https://patentgrep.com/patent/US9437816B2

## CPC

- H10N 70/841: {Electrodes}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/881: {Switching materials}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.

## Claims

### Claim 1

A memory cell, comprising:
a phase change material between a first electrode and a second electrode, wherein the phase change material includes contoured sidewalls that contact a first spacer and a second spacer, wherein the first and second spacers include contoured sidewalls, wherein the first spacer is in contact with a first insulator region and the second spacer is in contact with a second insulator region, wherein the first insulator region includes a first contoured sidewall and a second contoured sidewall and the second insulator region includes a third contoured sidewall, and wherein an adjacent memory cell is formed between the second contoured sidewall of the first insulator region and a third insulator region.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the phase change material contacts the first electrode in a self-aligned opening between the number of insulator regions.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein the first spacer and the second spacer further define the distance between the first insulator region and the second insulator region.

### Claim 4 (depends on 1)

The memory cell of claim 1, wherein an amount of phase change material in the memory device is defined by the distance between the number of spacers.

### Claim 5 (depends on 1)

The memory cell of claim 1, wherein the memory device is part of an array of memory devices.

### Claim 6 (depends on 1)

The memory cell of claim 1, wherein the memory device is insulated from the adjacent memory devices by a dielectric material that forms the second insulator region.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein a contact area between the phase change material and the first electrode is defined by the first spacer and the second spacer.

### Claim 8

A memory cell, comprising:
a phase change material in contact with a conductive material, wherein the conductive material contacts a first electrode in an opening between a first insulator region and a second insulator region, wherein the conductive material includes contoured sidewalls that contact a first spacer and a second spacer, wherein the first and second spacers include contoured sidewalls, wherein the first spacer is in contact with the first insulator region and the second spacer is in contact with the second insulator region, wherein the first insulator region includes a first contoured sidewall and the second insulator region includes a second contoured sidewall, and wherein the phase change material is between the first electrode and a second electrode.

### Claim 9 (depends on 8)

The memory cell of claim 8, wherein the conductive material is in a self-aligned opening between the number of insulator regions.

### Claim 10 (depends on 8)

The memory cell of claim 8, wherein the first spacer and the second spacer further define the distance between the first insulator region and the second insulator region.

### Claim 11 (depends on 8)

The memory cell of claim 8, wherein the phase change material contacts the conductive material at an upper surface of the conductive material between the first and second insulator regions that include the first and second spacers.

### Claim 12 (depends on 11)

The memory cell of claim 11, wherein a contact surface between the phase change material and the conductive material is defined by the distance between the first and second insulator regions.

### Claim 13 (depends on 8)

The memory device of claim 8, wherein a contact area between the first electrode and the conductive material is defined by the distance between the first and second spacers.

### Claim 14

An array of memory cells, comprising:
a first memory cell including a first phase change material between a first electrode and a second electrode, wherein the first phase change material is formed in a first self-aligned opening, wherein a contoured sidewall of the first phase change material contacts a first spacer, and wherein the first spacer is formed on a first contoured sidewall of a dielectric material;
a second memory cell including a second phase change material between a third electrode and a fourth electrode, wherein the second phase change material is formed in a second self-aligned opening, wherein a contoured sidewall of the second phase change material contacts a second spacer, and wherein the second spacer is formed on a second contoured sidewall of the dielectric material.

### Claim 15 (depends on 14)

The array of claim 14, wherein a contact area between the first electrode and the first phase change material is defined by the distance between the first spacer and another spacer.

### Claim 16 (depends on 14)

The array of claim 14, wherein the first phase change material is a Germanium-Antimony-Tellurium (GST) material.

### Claim 17 (depends on 14)

The array of claim 14, wherein the first spacer at least partially forms a contoured profile for the first opening.

### Claim 18 (depends on 14)

The array of claim 14, wherein the second electrode contacts the first phase change material at an upper surface of the phase change material.