# US 9,437,815 B1 · Resistive switching memory device architecture for reduced cell damage during processing

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- Number: US 9,437,815 B1
- Document ID: US9437815B1
- Status: Granted
- Kind: B1
- Application number: 14/265,548
- Filed: 2014-04-30
- Granted: 2016-09-06
- Earliest claimed: 2014-04-30
- Assignees: Adesto Technologies Corporation
- Applicants: Adesto Technologies Corporation
- Inventors: Ming Sang Kwan
- Web page: https://patentgrep.com/patent/US9437815B1

## CPC

- H10D 89/911: {using passive elements as protective elements}
- H10N 70/841: {Electrodes}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells arranged in a plurality of array blocks, where each resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction, and to be erased to a high resistance state by application of an erase voltage in a reverse bias direction; (ii) a plurality of anode plates corresponding to the plurality of array blocks, where each resistive memory cell can include a resistive storage element having an anode coupled to one of the anode plates; (iii) an inactive ring surrounding the plurality of anode plates, where the inactive ring can include a same material as each of the plurality of anode plates; and (iv) a plurality of boundary cells located under the inactive ring.

## Claims

### Claim 1

A method of making a resistive switching memory device, the method comprising:
a) forming a plurality of resistive memory cells arranged in a plurality of array blocks, wherein each resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction, and to be erased to a high resistance state by application of an erase voltage in a reverse bias direction;
b) forming a plurality of anode plates corresponding to the plurality of array blocks, wherein each resistive memory cell comprises a resistive storage element having an anode coupled to one of the anode plates;
c) forming an inactive ring surrounding the plurality of anode plates, wherein the inactive ring comprises a same material as each of the plurality of anode plates; and
d) forming a plurality of boundary cells located under the inactive ring.

### Claim 2 (depends on 1)

The method of claim 1 wherein the same material comprises a metal oxide.

### Claim 3 (depends on 1)

The method of claim 1, wherein the same material comprises an injection barrier layer (IBL).

### Claim 4 (depends on 1)

The method of claim 1, wherein the same material comprises titanium.

### Claim 5 (depends on 1)

The method of claim 1, wherein the same material comprises titanium nitride.

### Claim 6 (depends on 1)

The method of claim 1, wherein each resistive memory cell comprises n+ regions in a p-substrate.

### Claim 7 (depends on 6)

The method of claim 6, wherein each boundary cell comprises p+ regions in the p-substrate.

### Claim 8 (depends on 1)

The method of claim 1, further comprising connecting the inactive ring to a p-substrate of the resistive switching memory device.

### Claim 9 (depends on 1)

The method of claim 1, wherein the forming the plurality of anode plates and the inactive ring comprises:
a) depositing the same material on a surface of the resistive switching memory device;
b) patterning a hard mask layer on the same material to define regions for the plurality of anode plates and the inactive ring; and
c) using plasma etching to remove the same material from areas not covered by the patterned hard mask layer, wherein the plurality of boundary cells are configured to sink current from the plasma etching.

### Claim 10 (depends on 1)

The method of claim 1, wherein the resistive storage element comprises a conductive bridging random-access memory (CBRAM) storage element.