# US 9,437,814 B1 · Mitigating damage from a chemical mechanical planarization process

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- Number: US 9,437,814 B1
- Document ID: US9437814B1
- Status: Granted
- Kind: B1
- Application number: 14/473,879
- Filed: 2014-08-29
- Granted: 2016-09-06
- Earliest claimed: 2014-02-06
- Assignees: Crossbar, Inc.
- Applicants: Crossbar, Inc.
- Inventors: Harry Yue Gee; Majid Milani; Natividad Vasquez, Jr.; Steven Patrick Maxwell; Sundar Narayanan
- Web page: https://patentgrep.com/patent/US9437814B1

## CPC

- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/883: {Oxides or nitrides}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.

## Claims

### Claim 1

A method for removing damage from a terminal of a two-terminal memory device during fabrication of the two-terminal memory device, comprising:
forming the terminal of the two-terminal memory device comprising a monolithic stack of layers including the terminal, wherein the terminal is in contact with a metal interconnect layer that is situated in a dielectric layer;
forming an intermetal dielectric layer atop the dielectric layer and the terminal;
performing a chemical mechanical planarization (CMP) process to planarize the terminal with respect to the intermetal dielectric layer; and
performing a first post-CMP process for removing a damaged portion of the terminal resulting from the CMP process.

### Claim 2 (depends on 1)

The method of claim 1, wherein the two-terminal memory device is a resistive switching memory device.

### Claim 3 (depends on 1)

The method of claim 1, wherein the terminal comprises at least one of: p-type silicon (Si), doped p-type silicon germanium (SiGe) with a germanium (Ge) proportion of the terminal in a range of between about ten percent to about sixty percent, or a metal comprising at least one of tungsten (W), copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel (Ni), or molybdenum (Mo).

### Claim 4 (depends on 1)

The method of claim 1, wherein a height of the terminal is in a range of about 50 nanometers (nm) to about 300 nm.

### Claim 5 (depends on 1)

The method of claim 1, wherein a width of the terminal is in a range of about 10 nm to about 200 nm.

### Claim 6 (depends on 1)

The method of claim 1, wherein a top surface of the terminal has a surface height variation of less than about 10 nm after forming the terminal or after performing the first post-CMP process.

### Claim 7 (depends on 1)

The method of claim 1, wherein the intermetal dielectric layer comprises at least one of: silicon dioxide (SiO2), fluorine doped silicate glass (FSG), a low-K dielectric, or a nitride.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first post-CMP process is a light etching process that employs at least one of: plasma oxygen (O2) ash, sulfuric acid (H2SO4), hydrogen peroxide (H2O2), water (H2O), ozone (O3), hydrogen fluoride (HF), or ammonium hydroxide (NH4OH).

### Claim 9 (depends on 1)

The method of claim 1, further comprising a second post-CMP process for cleaning an exposed surface of the terminal.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second post-CMP process removes from the exposed surface of the terminal oxides resulting from the CMP process or the first post-CMP process.

### Claim 11 (depends on 9)

The method of claim 9, wherein the second post-CMP process employs HF in connection with the cleaning.

### Claim 12 (depends on 1)

The method of claim 1, further comprising forming a set of dummy elements on a wafer that includes an array of terminals comprising the terminal prior to the performing the CMP process, wherein the array includes the terminal, and the set of dummy elements are formed outside the array.

### Claim 13 (depends on 1)

The method of claim 1, further comprising:
forming, in the monolithic stack of layers, an interface layer comprising non-stoichiometric silicon compound comprising crystalline defects in contact with the terminal;
forming, in the monolithic stack of layers, an active metal layer in contact with the interface layer configured to provide filament forming particles comprising silver or aluminum to the crystalline defects within the interface layer comprising;
forming a second terminal of the two-terminal memory device; or
coupling the second terminal to the active metal layer.

### Claim 14

A method for mitigating damage to a terminal of a two-terminal memory device during fabrication of the two-terminal memory device, comprising:
forming the terminal of the two-terminal memory device, wherein the terminal is in contact with and patterned on a metal interconnect layer of the two-terminal memory device and the metal interconnect layer is situated in a dielectric layer;
forming a sacrificial layer atop the terminal;
forming an intermetal dielectric layer atop the dielectric layer and the sacrificial layer;
performing a chemical mechanical planarization (CMP) process to planarize the sacrificial layer with respect to the intermetal dielectric layer; and
performing a post-CMP removal process for removing the sacrificial layer from the terminal.

### Claim 15 (depends on 14)

The method of claim 14, wherein the terminal comprises at least one of: p-type silicon (Si), doped p-type silicon germanium (SiGe) with a germanium (Ge) proportion of the terminal in a range of between about ten percent to about sixty percent, or a metal comprising at least one of tungsten (W), copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel (Ni), or molybdenum (Mo).

### Claim 16 (depends on 14)

The method of claim 14, wherein a height of the terminal is in a range of about 50 nanometers (nm) to about 300 nm.

### Claim 17 (depends on 14)

The method of claim 14, wherein a width of the terminal is in a range of about 10 nm to about 200 nm.

### Claim 18 (depends on 14)

The method of claim 14, wherein a top surface of the terminal has a surface height variation of less than about 10 nm after forming the terminal or after performing the post-CMP removal process.

### Claim 19 (depends on 14)

The method of claim 14, wherein the sacrifical layer comprises at least one of: tungsten (W), titanium nitride (TiN), or a nitride.

### Claim 20 (depends on 14)

The method of claim 14, wherein the intermetal dielectric layer comprises at least one of: silicon dioxide (SiO2), fluorine doped silicate glass (FSG), a low-K dielectric, or a nitride.

### Claim 21 (depends on 14)

The method of claim 14, wherein the post-CMP process removes a portion of the sacrificial layer.

### Claim 22 (depends on 14)

The method of claim 14, wherein the post-CMP removal process comprises a dry etch process.

### Claim 23 (depends on 14)

The method of claim 14, wherein the post-CMP removal process comprises a wet etch process.

### Claim 24 (depends on 14)

The method of claim 14, further comprising:
forming an interface layer comprising a non-stoichiometric silicon compound in contact with the terminal;
forming an active metal layer in contact with the interface layer configured to provide filament forming particles to crystalline defects within the interface layer, wherein the filament forming particles comprise silver or aluminum;
forming another terminal of the two-terminal memory device; or
coupling the other terminal to the active metal layer.