# US 9,437,813 B2 · Method for forming resistance-switching memory cell with multiple electrodes using nano-particle hard mask > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,813 B2 - Document ID: US9437813B2 - Status: Granted - Kind: B2 - Application number: 13/767,649 - Filed: 2013-02-14 - Published: 2014-08-14 - Granted: 2016-09-06 - Earliest claimed: 2013-02-14 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk 3D LLC - Inventors: George Matamis; James K Kai; Vinod R Purayath; Yuan Zhang; Henry Chien - Web page: https://patentgrep.com/patent/US9437813B2 ## CPC - H10N 70/20: Multistable switching devices, e.g. memristors - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10N 70/011: {Manufacture or treatment of multistable switching devices} - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8418: {adapted for focusing electric field or current, e.g. tip-shaped} - H10N 70/8828: {Tellurides, e.g. GeSbTe} - H10N 70/883: {Oxides or nitrides} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels} - H10N 70/8845: {Carbon or carbides} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract In a fabrication process for reversible resistance-switching memory cells, a bottom electrode layer is coated with nano-particles. The nano-particles are used to etch the bottom electrode layer, forming multiple narrow, spaced apart bottom electrode structures for each memory cell. A resistance-switching material is then deposited between and above the bottom electrode structures, followed by a top electrode layer. Or, insulation is deposited between and above the bottom electrode structures, followed by planarizing and a wet etch to expose top surfaces of the bottom electrode structures, then deposition of the resistance-switching material and the top electrode layer. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower. ## Claims ### Claim 1 A method for fabricating a resistance-switching memory device, comprising: depositing nano-particles on a bottom electrode layer on a substrate; etching the bottom electrode layer using the nano-particles as a mask, the etching results in a plurality of raised structures in the bottom electrode layer; removing the nano-particles; depositing a resistance-switching material, a top of each raised structure is in contact with the resistance-switching material; and forming separate resistance-switching memory cells, each resistance-switching memory cell comprises more than one of the raised structures as a bottom electrode, a portion of the resistance-switching material and a top electrode. ### Claim 2 (depends on 1) The method of claim 1, wherein: each resistance-switching memory cell comprises a plurality of the raised structures as bottom electrodes. ### Claim 3 (depends on 1) The method of claim 1, wherein: the forming comprises depositing a top electrode layer and etching the top electrode layer, the resistance-switching material and the bottom electrode layer in two orthogonal directions to form each resistance-switching memory cell as a pillar and to form the top electrodes; and spaced apart conductive rails are subsequently deposited as control lines aligned with rows of the pillars and in electrical contact with the top electrodes. ### Claim 4 (depends on 1) The method of claim 1, wherein: the forming comprises etching the resistance-switching material and the bottom electrode layer in two orthogonal directions to form each resistance-switching memory cell as a pillar and depositing spaced apart conductive rails aligned with rows of the pillars, the top electrodes are provide by the spaced apart conductive rails. ### Claim 5 (depends on 1) The method of claim 1, wherein: the etching of the bottom electrode layer comprises etching to a bottom of the bottom electrode layer so that the plurality of raised structures in the bottom electrode layer are not joined to one another. ### Claim 6 (depends on 1) The method of claim 1, wherein: the etching of the bottom electrode layer comprises only partially etching the bottom electrode layer so that the plurality of raised structures are joined to one another at a bottom of the bottom electrode layer. ### Claim 7 (depends on 1) The method of claim 1, wherein: the depositing of the resistance-switching material causes the resistance-switching material to fill voids between the plurality of raised structures, and to cover tops of the plurality of raised structures. ### Claim 8 (depends on 7) The method of claim 7, wherein: the resistance-switching material is in a high resistance state when deposited. ### Claim 9 (depends on 1) The method of claim 1, further comprising, before the depositing the resistance-switching material: depositing an insulating material, the insulating material fills voids between the plurality of raised structures, and covers tops of the plurality of raised structures; and polishing to remove a portion of the insulating material which is above the tops of the plurality of raised structures; and etching to remove a residual of the insulating material which is above the tops of the plurality of raised structures, thereby exposing the tops of the plurality of raised structures while leaving portions of the insulating material in the voids. ### Claim 10 (depends on 9) The method of claim 9, wherein: the resistance-switching material is in a high or low resistance state when deposited. ### Claim 11 (depends on 1) The method of claim 1, further comprising, before the depositing the resistance-switching material: slimming the plurality of raised structures by forming oxidized surfaces of the plurality of raised structures and removing the oxidized surfaces. ### Claim 12 (depends on 1) The method of claim 1, wherein: the bottom electrode layer is above a steering element layer; each resistance-switching memory cell comprises a portion of the steering element layer; and the portions of the steering element layer are in electrical contact with spaced-apart conductive rails in a bottom wiring layer. ### Claim 13 (depends on 1) The method of claim 1, wherein: the bottom electrode layer comprises doped polysilicon. ### Claim 14 (depends on 1) The method of claim 1, wherein: each raised structure has a width of no more than 2-9 nm. ### Claim 15 (depends on 1) The method of claim 1, wherein: less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the more than one raised structures of the resistance-switching memory cell. ### Claim 16 A method for fabricating a resistance-switching memory device, comprising: depositing nano-particles on a bottom electrode layer on a substrate; etching the bottom electrode layer using the nano-particles as a mask, the etching results in a plurality of raised structures in the bottom electrode layer; removing the nano-particles; depositing an insulating material, the insulating material fills voids between the plurality of raised structures, and covers tops of the plurality of raised structures; polishing to remove a portion of the insulating material which is above the tops of the plurality of raised structures; etching to remove a residual of the insulating material which is above the tops of the plurality of raised structures, thereby exposing the tops of the plurality of raised structures while leaving portions of the insulating material in the voids; depositing a resistance-switching layer, a top of each raised structure is in contact with a bottom of the resistance-switching layer; and etching the resistance-switching layer and the bottom electrode layer in two orthogonal directions to form a plurality of resistance-switching memory cells, each resistance-switching memory cell comprises one or more of the raised structures as a bottom electrode and a portion of the resistance-switching layer as a resistance-switching material. ### Claim 17 (depends on 16) The method of claim 16, further comprising: before the etching, depositing a top electrode layer above the resistance-switching layer, the etching comprising etching the top electrode layer, and each resistance-switching memory cell comprises a portion of the top electrode layer as a top electrode. ### Claim 18 (depends on 16) The method of claim 16, wherein: each resistance-switching memory cell comprises a plurality of the raised structures as bottom electrodes. ### Claim 19 (depends on 16) The method of claim 16, wherein: less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more of the raised structures of the resistance-switching memory cell. ### Claim 20 A method for fabricating a resistance-switching memory device, comprising: depositing nano-particles on a bottom electrode layer on a substrate; etching the bottom electrode layer using the nano-particles as a mask, the etching results in a plurality of raised structures in the bottom electrode layer; removing the nano-particles; depositing a resistance-switching material, a top of each raised structure is in contact with the resistance-switching material; and forming separate resistance-switching memory cells, each resistance-switching memory cell comprises one or more of the raised structures as a bottom electrode, a portion of the resistance-switching material and a top electrode, wherein the nano-particles are coated in a ligand, and the method further comprises etching the ligands after the depositing the nano-particles and before the etching the bottom electrode layer.