# US 9,437,809 B2 · Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same

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- Number: US 9,437,809 B2
- Document ID: US9437809B2
- Status: Granted
- Kind: B2
- Application number: 14/290,477
- Filed: 2014-05-29
- Published: 2014-09-18
- Granted: 2016-09-06
- Earliest claimed: 2009-01-12
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Jun Liu; Gurtej Sandhu
- Web page: https://patentgrep.com/patent/US9437809B2

## CPC

- H10N 50/10: Magnetoresistive devices
- B82Y 25/00: Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
- B82Y 40/00: Manufacture or treatment of nanostructures
- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- H01F 10/3254: {the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]}
- H01F 10/3268: {the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn}
- H01F 10/329: {Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect}
- H01F 41/307: {insulating or semiconductive spacer}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H01F 41/306: {conductive spacer}
- Y10S 977/70: Nanostructure
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

## Claims

### Claim 1

A memory cell comprising:
a pinned ferromagnetic layer;
a nonmagnetic source layer formed on the pinned ferromagnetic layer;
an insulative layer formed on the nonmagnetic source layer, wherein the insulative layer comprises a thickness in the range of approximately 10-30 nm;
a free ferromagnetic layer formed on the insulative layer; and
nanochannels formed in the insulative layer, wherein each of the nanochannels is filled with a filament contact comprising material from the nonmagnetic source layer.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the filament contact is configured to decrease a cross sectional area of a programming current flow.

### Claim 3 (depends on 1)

The memory cell of claim 1, comprising an access transistor electrically coupled to the memory cell and configured to provide electrical access to the memory cell.

### Claim 4 (depends on 3)

The memory cell of claim 3, comprising a word line coupled to a gate of the access transistor.

### Claim 5 (depends on 1)

The memory cell of claim 1, comprising a bit line coupled to the memory cell.

### Claim 6 (depends on 3)

The memory cell of claim 3, comprising a source line coupled to a source or a drain of the access transistor.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein each of the nanochannels and filament contacts have random shapes.

### Claim 8 (depends on 1)

The memory cell of claim 1, wherein the nonmagnetic source layer comprises copper or silver.

### Claim 9

A memory cell comprising:
a pinned layer;
a nonmagnetic source layer formed on the pinned layer;
an insulative layer formed on the nonmagnetic source layer, wherein the insulative layer comprises a thickness in the range of approximately 10-30 nm;
a free layer formed on the insulative layer; and
a filament contact formed from the nonmagnetic source layer and formed through the insulative layer such that the filament contact is electrically coupled between the pinned layer and the free layer.

### Claim 10 (depends on 9)

The memory cell of claim 9, wherein the filament contact is non-uniform.

### Claim 11 (depends on 9)

The memory cell of claim 9, wherein the nonmagnetic source layer comprises a thickness in the range of approximately 5-15 nm.

### Claim 12 (depends on 9)

The memory cell of claim 9, wherein the insulative layer comprises SiN or SiC.

### Claim 13 (depends on 9)

The memory cell of claim 9, wherein the insulative layer comprises a chalcogenide material.

### Claim 14 (depends on 9)

The memory cell of claim 9, wherein the pinned layer comprises one of Co, Fe, Ni or its alloys, NiFe, CoFe, CoNiFe, or doped alloys CoX, CoFeX, CoNiFeX (X=B, Cu, Re, Ru, Rh, Hf, Pd, Pt, C), or Fe3O4, CrO2, NiMnS, PtMnSb, or BiFeO.

### Claim 15 (depends on 9)

The memory cell of claim 9, wherein the free layer comprises one of Co, Fe, Ni or its alloys, NiFe, CoFe, CoNiFe, or doped alloys CoX, CoFeX, CoNiFeX (X=B, Cu, Re, Ru, Rh, Hf, Pd, Pt, C), or Fe3O4, CrO2, NiMnS, PtMnSb, or BiFeO.

### Claim 16 (depends on 9)

The memory cell of claim 9, wherein the nonmagnetic source layer comprises copper or silver.

### Claim 17

A memory cell comprising:
a pinned layer;
a free layer;
an insulative layer formed between the pinned layer and the free layer, wherein the insulative layer comprises a thickness in the range of approximately 10-30 nm; and
a filament contact formed through the insulative layer such that the filament contact is electrically coupled between the pinned layer and the free layer, wherein the filament contact comprises a random shape.

### Claim 18 (depends on 17)

The memory cell of claim 17, comprising a nonmagnetic source layer formed between the pinned layer and the free layer.

### Claim 19 (depends on 18)

The memory cell of claim 18, wherein the filament contact is formed from the nonmagnetic source layer.

### Claim 20 (depends on 18)

The memory cell of claim 18, wherein the nonmagnetic source layer has a thickness in the range of approximately 5-15 nm.

### Claim 21 (depends on 17)

The memory cell of claim 17, comprising an antiferromagnetic layer directly adjacent to the pinned layer.