# US 9,437,799 B2 · Method of forming a CMOS-based thermoelectric device

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- Number: US 9,437,799 B2
- Document ID: US9437799B2
- Status: Granted
- Kind: B2
- Application number: 14/957,314
- Filed: 2015-12-02
- Published: 2016-06-02
- Granted: 2016-09-06
- Earliest claimed: 2014-05-30
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Henry Litzmann Edwards; Kenneth James Maggio; Toan Tran; Jihong Chen; Jeffrey R. Debord
- Web page: https://patentgrep.com/patent/US9437799B2

## CPC

- H10N 10/01: Manufacture or treatment
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10D 62/57: the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
- H10D 84/40: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence)
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10N 10/81: Structural details of the junction
- H10N 15/00: Thermoelectric devices without a junction of dissimilar materials; Thermomagnetic devices, e.g. using the Nernst-Ettingshausen effect (integrated devices or assemblies of multiple devices H10N19/00)
- H10N 19/00: Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

## Claims

### Claim 1

A method of forming an integrated circuit, the method comprising:
providing a substrate including silicon-based semiconductor material;
forming isolation trenches in the substrate between active areas of the integrated circuit to laterally isolate active areas for an NMOS transistor and a PMOS transistor in an area for CMOS transistors of the integrated circuit, and for n-type thermoelectric elements and p-type thermoelectric elements of an embedded thermoelectric device of the integrated circuit, the n-type thermoelectric elements and the p-type thermoelectric elements being less than 300 nanometers wide at a narrowest position;
subsequently implanting n-type dopants into the substrate to form an n-type region having a doping density of at least 1×1018 cm−3 which encompasses the n-type thermoelectric elements and the substrate between the n-type thermoelectric elements at least 100 nanometers below the isolation trenches, and implanting p-type dopants into the substrate to form a p-type region having a doping density of at least 1×1018 cm−3 which encompasses the p-type thermoelectric elements and the substrate between the p-type thermoelectric elements at least 100 nanometers below the isolation trenches;
subsequently forming dielectric material in the isolation trenches to provide field oxide of the integrated circuit; and
forming a metal interconnect structure which connects upper ends of the n-type thermoelectric elements and the p-type thermoelectric elements to a thermal node.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the isolation trenches further laterally isolate at least one active area for an n-type thermal tap of the embedded thermoelectric device adjacent to the n-type thermoelectric elements, the n-type region encompassing the n-type thermal tap; and
the isolation trenches further laterally isolate at least one active area for a p-type thermal tap of the embedded thermoelectric device adjacent to the p-type thermoelectric elements, the p-type region encompassing the p-type thermal tap.

### Claim 3 (depends on 1)

The method of claim 1, and comprising:
forming an n-type region mask over the substrate so as to expose the n-type thermoelectric elements and cover the p-type thermoelectric elements and the area for the CMOS transistors, after forming the isolation trenches and before implanting the n-type dopants; and
removing the n-type region mask after implanting the n-type dopants.

### Claim 4 (depends on 1)

The method of claim 1, and comprising:
forming a p-type region mask over the substrate so as to expose the p-type thermoelectric elements and cover the n-type thermoelectric elements and the area for the CMOS transistors, after forming the isolation trenches and before implanting the p-type dopants; and
removing the p-type region mask after implanting the p-type dopants.

### Claim 5 (depends on 1)

The method of claim 1, and comprising:
forming an n-type well mask over the substrate so as to expose the active area for the PMOS transistor and the n-type thermoelectric elements and to cover the active area for the NMOS transistor and the p-type thermoelectric elements;
implanting n-type dopants into the substrate in areas exposed by the n-type well mask; and
subsequently removing the n-type well mask.

### Claim 6 (depends on 1)

The method of claim 1, and comprising:
forming a p-type well mask over the substrate so as to expose the active area for the NMOS transistor and the p-type thermoelectric elements and to cover the active area for the PMOS transistor and the n-type thermoelectric elements;
implanting p-type dopants into the substrate in areas exposed by the p-type well mask; and
subsequently removing the p-type well mask.

### Claim 7 (depends on 1)

The method of claim 1, and comprising:
forming an n-channel source/drain (NSD) mask over the substrate so as to expose the active area for the NMOS transistor and the n-type thermoelectric elements and to cover the active area for the PMOS transistor and the p-type thermoelectric elements;
implanting n-type dopants into the substrate in areas exposed by the NSD mask; and
subsequently removing the NSD mask.

### Claim 8 (depends on 1)

The method of claim 1, and comprising:
forming a p-channel source/drain (PSD) mask over the substrate so as to expose the active area for the PMOS transistor and the p-type thermoelectric elements and to cover the active area for the NMOS transistor and the n-type thermoelectric elements;
implanting p-type dopants into the substrate in areas exposed by the PSD mask; and
subsequently removing the PSD mask.

### Claim 9

A method of forming an integrated circuit, the method comprising:
providing a substrate including silicon-based semiconductor material;
forming isolation trenches in the substrate between active areas of the integrated circuit to laterally isolate active areas for an NMOS transistor and a PMOS transistor in an area for CMOS transistors of the integrated circuit, and for n-type thermoelectric elements and p-type thermoelectric elements of an embedded thermoelectric device of the integrated circuit, the n-type thermoelectric elements and the p-type thermoelectric elements being less than 300 nanometers wide at a narrowest position;
subsequently forming dielectric material in the isolation trenches to provide field oxide of the integrated circuit;
implanting n-type dopants into the substrate to form an n-type region having a doping density of at least 1×1018 cm−3 which encompasses the n-type thermoelectric elements and the substrate between the n-type thermoelectric elements at least 100 nanometers below the isolation trenches;
implanting p-type dopants into the substrate to form a p-type region having a doping density of at least 1×1018 cm−3 which encompasses the p-type thermoelectric elements and the substrate between the p-type thermoelectric elements at least 100 nanometers below the isolation trenches; and
forming a metal interconnect structure which connects upper ends of the n-type thermoelectric elements and the p-type thermoelectric elements to a thermal node.

### Claim 10 (depends on 9)

The method of claim 9, wherein implanting the n-type dopants and implanting the p-type dopants is performed prior to forming the isolation trenches.

### Claim 11 (depends on 9)

The method of claim 9, wherein implanting the n-type dopants and implanting the p-type dopants is performed after forming the dielectric material in the isolation trenches.

### Claim 12 (depends on 9)

The method of claim 9, and comprising:
forming an n-type region mask over the substrate so as to expose the n-type thermoelectric elements and cover the p-type thermoelectric elements and the area for the CMOS transistors, before implanting the n-type dopants; and
removing the n-type region mask after implanting the n-type dopants.

### Claim 13 (depends on 9)

The method of claim 9, and comprising:
forming a p-type region mask over the substrate so as to expose the p-type thermoelectric elements and cover the n-type thermoelectric elements and the area for the CMOS transistors, before implanting the p-type dopants; and
removing the p-type region mask after implanting the p-type dopants.

### Claim 14 (depends on 9)

The method of claim 9, and comprising:
forming an n-type well mask over the substrate so as to expose the active area for the PMOS transistor and the n-type thermoelectric elements and to cover the active area for the NMOS transistor and the p-type thermoelectric elements;
implanting n-type dopants into the substrate in areas exposed by the n-type well mask; and
subsequently removing the n-type well mask.

### Claim 15 (depends on 9)

The method of claim 9, and comprising:
forming a p-type well mask over the substrate so as to expose the active area for the NMOS transistor and the p-type thermoelectric elements and to cover the active area for the PMOS transistor and the n-type thermoelectric elements;
implanting p-type dopants into the substrate in areas exposed by the p-type well mask; and
subsequently removing the p-type well mask.