# US 9,437,794 B2 · Method of fabricating a flip chip light emitting diode (FCLED) die having N-conductor layer

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- Number: US 9,437,794 B2
- Document ID: US9437794B2
- Status: Granted
- Kind: B2
- Application number: 15/017,707
- Filed: 2016-02-08
- Published: 2016-06-23
- Granted: 2016-09-06
- Earliest claimed: 2014-07-27
- Assignees: SemiLEDS Optoelectronics Co., Ltd.
- Applicants: SemiLEDS Optoelectronics Co., Ltd.
- Inventors: Yi-Feng Shih
- Web page: https://patentgrep.com/patent/US9437794B2

## CPC

- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10H 20/01: Manufacture or treatment
- H10H 20/01335: {the light-emitting regions comprising nitride materials}
- H10H 20/812: within the light-emitting regions, e.g. having quantum confinement structures
- H10H 20/814: having reflecting means, e.g. semiconductor Bragg reflectors
- H10H 20/821: of the light-emitting regions, e.g. non-planar junctions
- H10H 20/825: containing nitrogen, e.g. GaN
- H10H 20/831: characterised by their shape
- H10H 20/8312: {extending at least partially through the bodies}
- H10H 20/84: Coatings, e.g. passivation layers or antireflective coatings
- H10H 20/856: Reflecting means
- H10H 20/032: {of electrodes}
- H10H 20/036: {of packages}
- H10H 20/0363: {of optical field-shaping means}
- H10H 20/0364: {of interconnections}
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

A method for fabricating a flip chip light emitting diode (FCLED) die includes forming an epitaxial stack on a carrier substrate having an n-type confinement layer, a multiple quantum well (MQW) layer, and a p-type confinement layer, forming a mirror layer on the p-type confinement layer, forming an n-trench in the n-type confinement layer, forming an n-conductor layer in the n-trench on the n-type confinement layer, forming a p-metal layer on the p-type confinement layer, forming a first electrical isolator layer on the n-conductor layer and a second electrical isolator layer on the p-metal layer, forming a p-pad on the first electrical isolator layer, and forming an n-pad the second electrical isolator layer.

## Claims

### Claim 1

A method for fabricating a flip chip light emitting diode (FCLED) die comprising:
forming an epitaxial stack on a carrier substrate having an n-type confinement layer, a multiple quantum well (MQW) layer on the n-type confinement layer configured to emit electromagnetic radiation, and a p-type confinement layer on the multiple quantum well (MQW) layer;
forming a mirror layer on the p-type confinement layer;
forming an n-conductor layer on the n-type confinement layer and a p-metal layer on the p-type confinement layer;
forming a first electrical isolator layer on the n-conductor layer and a second electrical isolator layer on the p-metal layer;
forming a p-pad on the first electrical isolator layer electrically isolated from the n-conductor layer by the first electrical isolator layer; and
forming an n-pad on the second electrical isolator layer in electrical contact with the n-conductor layer and electrically isolated from the p-metal layer by the second electrical isolator layer.

### Claim 2 (depends on 1)

The method of claim 1 further comprising forming an n-trench in the n-type confinement layer and the forming the n-conductor layer step forms the conductor layer as a conductive trace in the trench having an n-end in electrical contact with the n-pad, and a p-end located subjacent to but electrically isolated from the p-pad.

### Claim 3 (depends on 1)

The method of claim 1 wherein the p-pad and the n-pad are separated by a gap having a WG and the n-conductor layer comprises a conductive trace spanning the gap.

### Claim 4 (depends on 1)

The method of claim 1 wherein the p-pad has a width of WP, the n-pad has a width of WN and the n-conductor layer comprises a conductive trace having a length (L) configured to allow the width WP and the width WN to be adjusted.

### Claim 5 (depends on 1)

The method of claim 1 wherein the n-pad comprises a plurality of n-pads and the n-conductor layer comprises a plurality of n-conductor layers configured as conductive traces in electrical contact with the n-pads.

### Claim 6

A method for fabricating a flip chip light emitting diode (FCLED) die comprising:
providing an epitaxial stack comprising a p-type confinement layer, a multiple quantum well (MQW) layer in electrical contact with the p-type confinement layer configured to emit electromagnetic radiation, and an n-type confinement layer in electrical contact with the multiple quantum well (MQW) layer having a trench;
forming a mirror layer on the p-type confinement layer;
forming a p-metal layer on the mirror layer in electrical contact with the p-type confinement layer;
forming a p-pad in electrical communication with the p-type confinement layer via the p-metal layer;
forming an n-pad in electrical contact with the n-type confinement layer via an n-contact area;
forming an n-conductor layer in electrical contact with the n-type confinement layer configured to increase the n-contact area between the n-pad and the n-type confinement layer;
forming a first electrical isolator layer on the n-conductor layer configured to electrically insulate the n-conductor layer from the p-pad; and
forming a second electrical isolator layer on the p-type confinement layer configured to electrically insulate the n-pad from the p-metal layer,
wherein the p-pad has a width of WP, the n-pad has a width of WN and the n-conductor layer comprises a conductive trace having a length (L) configured to allow the width WP and the width WN to be adjusted.

### Claim 7 (depends on 6)

The method of claim 6 wherein the p-pad and the n-pad are separated by a gap having a WG and the n-conductor layer comprises a conductive trace spanning the gap.

### Claim 8 (depends on 6)

The method of claim 6 wherein the conductive trace includes an n-end in electrical contact with the n-pad, and a p-end located subjacent to the p-pad.

### Claim 9 (depends on 6)

The method of claim 6 wherein the n-pad comprises a plurality of n-pads and the n-conductor layer comprises a plurality of n-conductor layers configured as conductive traces in electrical contact with the n-pads.

### Claim 10 (depends on 6)

The method of claim 6 wherein the p-pad has a width of WP, the n-pad has a width of WN and the n-conductor layer comprises a conductive trace having a length (L) configured to allow the width WP and the width WN to be adjusted.