# US 9,437,748 B2 · Method for manufacturing semiconductor device

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- Number: US 9,437,748 B2
- Document ID: US9437748B2
- Status: Granted
- Kind: B2
- Application number: 14/945,937
- Filed: 2015-11-19
- Published: 2016-03-17
- Granted: 2016-09-06
- Earliest claimed: 2008-08-08
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Hidekazu Miyairi; Kengo Akimoto; Yasuo Nakamura
- Web page: https://patentgrep.com/patent/US9437748B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6723: {having light shields}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/402: {Amorphous materials}
- H10D 62/80: characterised by the materials
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/40: of conductive or resistive materials
- H10P 14/6519: {the substance being oxygen}
- H10P 50/20: Dry etching; Plasma etching; Reactive-ion etching
- H10P 50/69: {using masks for semiconductor materials}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P 95/70: Chemical treatments
- H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

## Claims

### Claim 1

A semiconductor device comprising:
a gate electrode;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer;
a second conductive layer over the oxide semiconductor layer;
a first oxide between the oxide semiconductor layer and the first conductive layer, the first oxide including titanium; and
a second oxide between the oxide semiconductor layer and the second conductive layer, the second oxide including titanium,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region is in contact with the insulating layer,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein a length of the first oxide in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer, and
wherein a length of the second oxide in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the gate electrode includes aluminum, chromium, titanium, tantalum, molybdenum, or copper.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein each of the first oxide and the second oxide has n-type conductivity.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the second gate insulating layer contains excessive oxygen.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains excessive oxygen.

### Claim 8

A semiconductor device comprising:
a gate electrode;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer;
a second conductive layer over the oxide semiconductor layer;
a first oxide between the oxide semiconductor layer and the first conductive layer, the first oxide including titanium; and
a second oxide between the oxide semiconductor layer and the second conductive layer, the second oxide including titanium,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region is in contact with the insulating layer,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein the gate electrode has a light-shielding property,
wherein a length of the first oxide in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer, and
wherein a length of the second oxide in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein the gate electrode includes aluminum, chromium, titanium, tantalum, molybdenum, or copper.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8, wherein each of the first oxide and the second oxide has n-type conductivity.

### Claim 12 (depends on 8)

The semiconductor device according to claim 8,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.

### Claim 13 (depends on 8)

The semiconductor device according to claim 8, wherein the second gate insulating layer contains excessive oxygen.

### Claim 14 (depends on 8)

The semiconductor device according to claim 8, wherein the oxide semiconductor layer contains excessive oxygen.

### Claim 15

A semiconductor device comprising:
a gate electrode;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer;
a second conductive layer over the oxide semiconductor layer;
a first oxide between the oxide semiconductor layer and the first conductive layer, the first oxide including titanium; and
a second oxide between the oxide semiconductor layer and the second conductive layer, the second oxide including titanium,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region is in contact with the insulating layer,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein the gate electrode has a light-shielding property,
wherein each of the first gate insulating layer and the second gate insulating layer has a light-transmitting property,
wherein a length of the first oxide in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer, and
wherein a length of the second oxide in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, wherein the gate electrode includes aluminum, chromium, titanium, tantalum, molybdenum, or copper.

### Claim 17 (depends on 15)

The semiconductor device according to claim 15, wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.

### Claim 18 (depends on 15)

The semiconductor device according to claim 15, wherein each of the first oxide and the second oxide has n-type conductivity.

### Claim 19 (depends on 15)

The semiconductor device according to claim 15,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.

### Claim 20 (depends on 15)

The semiconductor device according to claim 15, wherein the second gate insulating layer contains excessive oxygen.

### Claim 21 (depends on 15)

The semiconductor device according to claim 15, wherein the oxide semiconductor layer contains excessive oxygen.

### Claim 22

A semiconductor device comprising:
a gate electrode;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer;
a second conductive layer over the oxide semiconductor layer;
a first layer between the oxide semiconductor layer and the first conductive layer, the first layer including titanium; and
a second layer between the oxide semiconductor layer and the second conductive layer, the second layer including titanium,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region is in contact with the insulating layer,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein a length of the first layer in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer, and
wherein a length of the second layer in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer.

### Claim 23 (depends on 22)

The semiconductor device according to claim 22, wherein the gate electrode includes aluminum, chromium, titanium, tantalum, molybdenum, or copper.

### Claim 24 (depends on 22)

The semiconductor device according to claim 22, wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.

### Claim 25 (depends on 22)

The semiconductor device according to claim 22, wherein each of the first layer and the second layer has n-type conductivity.

### Claim 26 (depends on 22)

The semiconductor device according to claim 22, wherein the insulating layer overlaps the gate electrode, wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and wherein the region of the oxide semiconductor layer does not overlap the gate electrode.

### Claim 27 (depends on 22)

The semiconductor device according to claim 22, wherein the second gate insulating layer contains excessive oxygen.

### Claim 28 (depends on 22)

The semiconductor device according to claim 22, wherein the oxide semiconductor layer contains excessive oxygen.

### Claim 29 (depends on 22)

The semiconductor device according to claim 22, wherein each of the first layer and the second layer includes oxygen.

### Claim 30

A semiconductor device comprising:
a gate electrode;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer;
a second conductive layer over the oxide semiconductor layer;
a first layer between the oxide semiconductor layer and the first conductive layer, the first layer including titanium; and
a second layer between the oxide semiconductor layer and the second conductive layer, the second layer including titanium,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region is in contact with the insulating layer,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein the gate electrode has a light-shielding property, wherein a length of the first layer in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer, and
wherein a length of the second layer in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer.

### Claim 31 (depends on 30)

The semiconductor device according to claim 30, wherein the gate electrode includes aluminum, chromium, titanium, tantalum, molybdenum, or copper.

### Claim 32 (depends on 30)

The semiconductor device according to claim 30, wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.

### Claim 33 (depends on 30)

The semiconductor device according to claim 30, wherein each of the first layer and the second layer has n-type conductivity.

### Claim 34 (depends on 30)

The semiconductor device according to claim 30,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.

### Claim 35 (depends on 30)

The semiconductor device according to claim 30, wherein the second gate insulating layer contains excessive oxygen.

### Claim 36 (depends on 30)

The semiconductor device according to claim 30, wherein the oxide semiconductor layer contains excessive oxygen.

### Claim 37 (depends on 30)

The semiconductor device according to claim 30, wherein each of the first layer and the second layer includes oxygen.

### Claim 38

A semiconductor device comprising:
a gate electrode;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer;
a second conductive layer over the oxide semiconductor layer;
a first layer between the oxide semiconductor layer and the first conductive layer, the first layer including titanium; and
a second layer between the oxide semiconductor layer and the second conductive layer, the second layer including titanium,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region is in contact with the insulating layer,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein the gate electrode has a light-shielding property, wherein each of the first gate insulating layer and the second gate insulating layer has a light-transmitting property,
wherein a length of the first layer in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer, and
wherein a length of the second layer in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer.

### Claim 39 (depends on 38)

The semiconductor device according to claim 38, wherein the gate electrode includes aluminum, chromium, titanium, tantalum, molybdenum, or copper.

### Claim 40 (depends on 38)

The semiconductor device according to claim 38, wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.

### Claim 41 (depends on 38)

The semiconductor device according to claim 38, wherein each of the first layer and the second layer has n-type conductivity.

### Claim 42 (depends on 38)

The semiconductor device according to claim 38, wherein the insulating layer overlaps the gate electrode, wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and wherein the region of the oxide semiconductor layer does not overlap the gate electrode.

### Claim 43 (depends on 38)

The semiconductor device according to claim 38, wherein the second gate insulating layer contains excessive oxygen.

### Claim 44 (depends on 38)

The semiconductor device according to claim 38, wherein the oxide semiconductor layer contains excessive oxygen.

### Claim 45 (depends on 38)

The semiconductor device according to claim 38, wherein each of the first layer and the second layer includes oxygen.