# US 9,437,742 B2 · Thin film transistor, manufacturing method thereof and array substrate

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- Number: US 9,437,742 B2
- Document ID: US9437742B2
- Status: Granted
- Kind: B2
- Application number: 14/348,802
- Filed: 2013-09-27
- Published: 2015-03-26
- Granted: 2016-09-06
- Earliest claimed: 2013-04-24
- Assignees: Beijing Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Applicants: Beijing Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Inventors: ChangJiang Yan; Jun Long; Xiaohui Zhu; Zhenyu Xie; Xu Chen
- Web page: https://patentgrep.com/patent/US9437742B2

## CPC

- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A thin film transistor, a manufacturing method thereof and an array substrate are provided. The thin film transistor includes: a gate electrode (102) formed on a substrate (101), a gate insulating layer (103) formed on the gate electrode (102) and covering at least a part of the substrate (101), and a semiconductor layer (105′), a source electrode (107a) and a drain electrode (107b) which are formed on the gate insulating layer (103). The material of the semiconductor layer (105′) is an oxide semiconductor; and the material of the source electrode (107a) and drain electrode (107b) is the oxide semiconductor which is doped. The source electrode (107a), the drain electrode (107b) and the semiconductor layer (105′) are disposed in the same layer.

## Claims

### Claim 1

A manufacturing method of a thin film transistor comprising steps of:
forming a gate electrode on a substrate;
forming a gate insulating layer on the gate electrode and at least a part of the substrate;
forming a non-crystalline oxide semiconductor thin film layer on the gate insulating layer;
forming a barrier layer on the non-crystalline oxide semiconductor thin film layer;
depositing a highly doped semiconductor thin film directly onto two portions of the oxide semiconductor thin film layer which are located on two opposite sides of the barrier layer and not covered by the barrier layer to increase carrier concentration at the interface between the non-crystalline oxide semiconductor thin film layer and the non-crystalline silicon thin film, so that the portions of the non-crystalline oxide semiconductor thin film layer at the interface exhibit electrical characteristics of conductor and thus form source and drain electrodes respectively,
wherein the highly doped semiconductor thin film is a highly doped hydrogenated non-crystalline silicon thin film.

### Claim 2 (depends on 1)

The manufacturing method of the thin film transistor of claim 1, further comprising forming a signal terminal in direct contact with the drain electrode, wherein the signal terminal includes a P-type layer, a I-type layer and a N-type layer,
the highly doped hydrogenated non-crystalline silicon layer directly on the drain electrode forms the P-type layer of the signal terminal.

### Claim 3 (depends on 2)

The manufacturing method of the thin film transistor of claim 2, wherein the step of forming the signal terminal in direct contact with the drain electrode comprises:
sequentially forming the I-type layer and the N-type layer on the P-type layer, wherein the I-type layer is formed of intrinsic silicon and the N-type layer is formed of N-type doped silicon.

### Claim 4 (depends on 2)

The manufacturing method of the thin film transistor of claim 2, further comprising:
forming a conducting layer on the signal terminal.

### Claim 5 (depends on 4)

The manufacturing method of the thin film transistor of claim 4, further comprising:
forming a first passivation layer on the conducting layer;
forming a first via hole and a second via hole in the first passivation layer, wherein the first via hole corresponds to the region of the drain electrode, and the second via hole corresponds to the region of the source electrode.

### Claim 6 (depends on 5)

The manufacturing method of the thin film transistor of claim 5, further comprising:
forming a first electrode and a second electrode on the first passivation layer, and forming a second passivation layer on the first electrode and the second electrode, wherein the first electrode is electrically connected with the conducting layer through the first via hole, and the second electrode is electrically connected with the source electrode through the second via hole.