# US 9,437,738 B2 · Field effect transistor with heterostructure channel

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- Number: US 9,437,738 B2
- Document ID: US9437738B2
- Status: Granted
- Kind: B2
- Application number: 14/175,341
- Filed: 2014-02-07
- Published: 2015-08-13
- Granted: 2016-09-06
- Earliest claimed: 2014-02-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chien-Ming Lin
- Web page: https://patentgrep.com/patent/US9437738B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/435: {having multiple laterally adjacent 1D material channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/123: {comprising junctions}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

In some embodiments, an FET structure comprises a heterostructure, and a gate structure. The heterostructure comprises a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least portions of source and drain regions, respectively. When the channel region is p type, the barrier section has a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section has a positive conduction band offset with respect to each of the first section and the second section. A gate structure is configured over the channel region.

## Claims

### Claim 1

A field effect transistor (FET) structure, comprising:
a heterostructure comprising:
a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least a portion of a first source or drain region and at least a portion of a second source or drain region, respectively,
a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the first section and the second section; and
a gate structure configured over the channel region;
wherein the heterostructure forms a nanowire structure suspended over a surface of a substrate;
wherein:
for the p type channel region,
the barrier section is formed of Si1-xGex, and
the first section and the second section are formed of Si1-yGey, where 0≦x<y≦1; or
for the n type channel region,
the barrier section is formed of SixGe1-x, and
the first section and the second section are formed of SiyGe1-y, where 0≦x<y≦1.

### Claim 2 (depends on 1)

The FET structure of claim 1, wherein:
the heterostructure forms at least a portion of a fin structure protruding from the surface of the substrate; and
the gate structure wraps around the channel region.

### Claim 3 (depends on 1)

The FET structure of claim 1, wherein:
the first section and the second section of the hetero structure are strained by a portion of the fin structure beneath the heterostructure; and
the barrier section has the same material as the portion of the fin structure beneath the heterostructure.

### Claim 4 (depends on 1)

The FET structure of claim 1, wherein:
the heterostructure is formed in a layer over a surface of a substrate; and
the gate structure is configured over the channel region.

### Claim 5 (depends on 1)

The FET structure of claim 1, wherein:
the gate structure wraps around the channel region.

### Claim 6

A field effect transistor (FET) structure, comprising:
a heterostructure comprising:
a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least a portion of a first source or drain region and at least a portion of a second source or drain region, respectively,
a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the first section and the second section; and
a gate structure configured over the channel region;
wherein the heterostructure forms a nanowire structure suspended over a surface of a substrate;
wherein:
for the p type channel region,
the barrier section is formed of GaAs1-xSbx, and
the first section and the section are formed of GaAs1-ySby, where 0≦x<y≦1; or
for the n type channel region,
the barrier section is formed of InxGa1-xAs, and
the first section and the section are formed of InyGa1-yAs or GaAs1-ySby, where 0≦x<y≦1.

### Claim 7

A method, comprising:
providing a first layer;
removing a first section and a second section of the first layer such that a barrier section between the first section and the second section remains;
epitaxially growing a third section and a fourth section in place of the first section and the second section,
a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the third section and the fourth section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the third section and the fourth section; and
forming a gate structure over a portion of the third section, the barrier section, and the fourth section;
wherein:
providing a first layer comprises:
forming a nanowire structure suspended over a surface of a substrate by pad regions,
the nanowire structure comprising the first layer; and
forming a sacrificial gate structure wrapping around a portion of the nanowire structure;
removing a first section and a second section of the first layer comprises:
removing the pad regions and the first section and the second section of the first layer; and
forming a gate structure over a portion of the third section, the barrier section, and the fourth section comprises:
forming a gate structure in place of the sacrificial gate structure.

### Claim 8

A method, comprising:
providing a first layer;
removing a first section and a second section of the first layer such that a barrier section between the first section and the second section remains;
epitaxially growing a third section and a fourth section in place of the first section and the second section,
a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the third section and the fourth section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the third section and the fourth section; and
forming a gate structure over a portion of the third section, the barrier section, and the fourth section;
wherein:
removing a first section and a second section of the first layer comprises:
forming a hard mask over a portion of the first section, the barrier section and a portion of the second section;
etching portions of the first layer on two sides of the hard mask;
converting the portion of the first section, the portion of the second section into a selectively etchable material with respect to a material of the barrier section; and
etching the converted portion of the first section and the portion of the section.

### Claim 9 (depends on 8)

The method of claim 8, wherein:
providing a first layer comprises:
forming a fin structure protruding from a surface of a substrate,
the fin structure comprising the first layer; and
forming a gate structure over a portion of the third section, the barrier section, and the fourth section comprises:
forming the gate structure wrapping around the portion of the third section, the barrier section, and the portion of the fourth section.

### Claim 10 (depends on 8)

The method of claim 8, wherein:
providing a first layer comprises:
providing a substrate or forming the first layer over a surface of a substrate; and
forming a gate structure over a portion of the third section, the barrier section, and the fourth section comprises:
forming the gate structure over the portion of the third section, the barrier section, and the portion of the fourth section.

### Claim 11 (depends on 8)

The method of claim 8, wherein:
for the p-type channel region,
providing a first layer comprises:
providing the first layer formed of Si1-xGex; and
epitaxially growing a third section and a fourth section in place of the first section and the second section comprises:
providing the third section and the forth section formed of Si1-yGey, where 0≦x<y≦1; or
for the n-type channel region,
providing a first layer comprises:
providing the first layer formed of SixGe1-x; and
epitaxially growing a third section and a fourth section in place of the first section and the second section comprises:
providing the third section and the forth section formed of SiyGe1-y, where 0≦x<y≦1.

### Claim 12 (depends on 8)

The method of claim 8, wherein:
converting the portion of the first section, the portion of the second section and the remaining portions of the first layer on the two sides of the hard mask into a selectively etchable material with respect to a material of the barrier section comprises:
oxidizing the portion of the first section, the portion of the second section and the remaining portions of the first layer on the two sides of the hard mask.

### Claim 13

A semiconductor structure, comprising:
a heterostructure comprising:
a barrier section forming heterojunctions with a first section and a second section, respectively,
a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the first section and the second section;
a gate structure configured over a portion of the heterostructure comprising the heterojunctions,
the gate structure comprising a dielectric layer, and a gate electrode stacked over the dielectric layer; and
a first doping region and a second doping region configured in the first section and the second section on opposite sides of the gate structure, respectively,
each of the first doping region and the second doping region having an opposite conductivity type with respect to the portion of the heterostructure over which the gate structure is configured;
wherein the heterostructure forms a nanowire structure suspended over a surface of a substrate.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein:
the heterostructure forms at least a portion of a fin structure protruding from the surface of the substrate; and
the gate structure wraps around the portion of the heterostructure comprising the heterojunctions.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein:
the first section and the second section of the hetero structure are strained by a portion of the fin structure beneath the heterostructure; and
the barrier section has the same material as the portion of the fin structure beneath the heterostructure.

### Claim 16 (depends on 13)

The semiconductor structure of claim 13, wherein:
the heterostructure is formed in a layer over a surface of a substrate; and
the gate structure is configured over the portion of the heterostructure comprising the heterojunctions.

### Claim 17 (depends on 13)

The semiconductor structure of claim 13, wherein:
the gate structure wraps around the portion of the heterostructure comprising the heterojunctions.

### Claim 18 (depends on 13)

The semiconductor structure of claim 13, wherein:
for the p type channel region,
the barrier section is formed of Si1-xGex, and
the first section and the second section are formed of Si1-yGey, where 0≦x<y≦1; or
for the n type channel region,
the barrier section is formed of SixGe1-x, and
the first section and the second section are formed of SiyGe1-y, where 0≦x<y≦1.