# US 9,437,737 B2 · Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device

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- Number: US 9,437,737 B2
- Document ID: US9437737B2
- Status: Granted
- Kind: B2
- Application number: 14/665,969
- Filed: 2015-03-23
- Published: 2015-07-09
- Granted: 2016-09-06
- Earliest claimed: 2004-06-24
- Assignees: Fujitsu Semiconductor Limited
- Applicants: Fujitsu Semiconductor Limited
- Inventors: Hidenobu Fukutome; Tomohiro Kubo
- Web page: https://patentgrep.com/patent/US9437737B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 30/225: {of a molecular ion, e.g. decaborane}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.

## Claims

### Claim 1

A semiconductor device comprising:
a silicon substrate;
a gate insulating film formed on the silicon substrate;
a gate electrode formed on the gate insulating film;
a source/drain region formed in the silicon substrate;
a SiGe layer formed in a hole in the source/drain region;
a sidewall formed on the side of the gate electrode,
an insulating film formed over the gate electrode and the SiGe layer; and
a conductive plug formed in the insulating film and electrically connected to the SiGe layer, wherein
a first side surface of the hole is located under the sidewall,
the SiGe layer is located under the sidewall and is not located under the gate electrode;
the first side surface includes two crystal planes,
a cross-sectional shape of the first side surface is concave,
each of the two crystal planes of the first side surface is defined by a (111) plane of the silicon substrate, and
an upper surface of the SiGe layer is located higher than an interface between the silicon substrate and the gate insulating film.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
one of the two crystal planes is connected to the surface of the silicon substrate, and
another of the two crystal planes is connected to a bottom surface of the hole.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1 further comprising:
a channel region in the silicon substrate under the gate electrode, wherein
the source/drain region is located between the (111) plane of the silicon substrate and the channel region.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a silicide layer formed between the SiGe layer and the conductive plug,
wherein a bottom surface of the silicide layer is located higher than an interface between the silicon substrate and the gate insulating film.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the silicide layer includes Pt.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising
a silicide layer formed over the SiGe layer,
wherein a second side surface of the hole that faces the first side surface is composed of the silicon substrate.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein
the second side surface includes two crystal planes, and
each of the two crystal planes of the second side surface is defined by a (111) plane of the silicon substrate.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6, wherein the silicide layer includes Pt.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein
the source/drain region is formed by implanting an impurity into the silicon substrate, and
the hole is formed by etching the source/drain region including the impurity.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the SiGe layer has a Ge concentration of 3 to 30%.