# US 9,437,736 B2 · Non-volatile semiconductor memory device

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- Number: US 9,437,736 B2
- Document ID: US9437736B2
- Status: Granted
- Kind: B2
- Application number: 14/215,536
- Filed: 2014-03-17
- Published: 2014-09-25
- Granted: 2016-09-06
- Earliest claimed: 2013-03-19
- Assignees: Floadia Corporation
- Applicants: Floadia Corporation
- Inventors: Yasuhiro Taniguchi; Kosuke Okuyama
- Web page: https://patentgrep.com/patent/US9437736B2

## CPC

- H10D 30/711: {having floating bodies}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In a non-volatile semiconductor memory device, it is only necessary that, at the time of data writing, a voltage drop is caused in a high resistance region. Therefore, the value of voltage applied to a gate electrode can be reduced as compared with a conventional device. In correspondence with the reduction in the value of applied voltage, it is possible to reduce the film thickness of a gate insulating film of memory transistors, and further the film thickness of the gate insulating film of a peripheral transistor for controlling the memory transistors. As a result, the circuit configuration of the non-volatile semiconductor memory device can be reduced in size as compared with the conventional device.

## Claims

### Claim 1

A non-volatile semiconductor memory device including one or more memory transistors each having a single layer gate structure in which a gate electrode is provided on a substrate via a gate insulating film, wherein
the memory transistor comprises:
a drain region formed in a surface of the substrate and connected to a bit line to which a write voltage is applied;
a source region formed in the surface of the substrate and connected to a source line to which a write source voltage higher than the write voltage applied to the drain region via the bit line is applied;
a carrier storage region provided on the substrate and arranged between the gate electrode and the drain region;
a channel region formed under the gate electrode, in which current flows by applying the write source voltage higher than the write voltage applied to the drain region to the source region via the source line and applying a write gate voltage to the gate electrode via a word line; and
a high resistance region formed in a region in the surface of the substrate being in contact with the drain region connected to the bit line to which the write voltage lower than the write source voltage applied to the source region is applied, facing the carrier storage region, and having a resistance value higher than a resistance value of a region between the source region and the channel region under the gate electrode;
wherein when current flows in the channel region by applying the write gate voltage to the gate electrode while applying the write source voltage higher than the write voltage applied to the drain region to the source region, current flows in the high resistance region as well, and a strong electric field is generated in the high resistance region due to a large voltage difference with respect to the drain region, thereby accelerating carriers in the drain region to be injected into the carrier storage region.

### Claim 2 (depends on 1)

The non-volatile semiconductor memory device according to claim 1, wherein
in the substrate, an extension region is formed in contact with the source region, and the high resistance region is formed to have an impurity concentration lower than the impurity concentration of the extension region.

### Claim 3 (depends on 1)

The non-volatile semiconductor memory device according to claim 1, wherein the high resistance region is formed in a region ranging from the drain region to a part of the channel region.

### Claim 4 (depends on 1)

The non-volatile semiconductor memory device according to claim 1, wherein a read voltage is applied to a bit line connected to the drain region, and whether or not carriers are injected into the carrier storage region is determined from a change of the read voltage at a time when the channel is formed by applying a voltage to the gate electrode.

### Claim 5 (depends on 1)

The non-volatile semiconductor memory device according to claim 1, wherein a film thickness of the gate insulating film of the memory transistor is selected to be equal to a smallest film thickness of the gate insulating film among peripheral transistors for controlling the memory transistor.

### Claim 6

A non-volatile semiconductor memory device, comprising:
at least one memory transistor comprising
a drain region formed in a surface of a substrate and connected to a bit line to which a write voltage is applied,
a source region formed in the surface of the substrate and connected to a source line to which a write source voltage higher than the write voltage is applied,
a carrier storage region provided on the substrate and arranged between a gate electrode and the drain region,
a channel region formed under the gate electrode and in which current flows by applying the write source voltage to the source region via the source line and by applying a write gate voltage to the gate electrode via a word line, and
a high resistance region formed in the surface of the substrate so as to be in contact with the drain region and so as to face the carrier storage region, where the high resistance region has a resistance value higher than a resistance value of a region between the source region and the channel region under the gate electrode;
wherein (a) current flows in the high resistance region when current flows in the channel region, and (b) a strong electric field is generated in the high resistance region due to a large voltage difference with respect to the drain region, thereby accelerating carriers in the drain region to be injected into the carrier storage region.