# US 9,437,735 B1 · Tunnel FET

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- Number: US 9,437,735 B1
- Document ID: US9437735B1
- Status: Granted
- Kind: B1
- Application number: 14/824,737
- Filed: 2015-08-12
- Granted: 2016-09-06
- Earliest claimed: 2015-05-13
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Akira Hokazono; Yoshiyuki Kondo
- Web page: https://patentgrep.com/patent/US9437735B1

## CPC

- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10D 12/211: {Gated diodes}
- H10D 62/141: {Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/834: further characterised by the dopants
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to one embodiment, a tunnel FET includes a semiconductor region of a first conductivity type, a gate electrode provided on a surface portion of the semiconductor region via a gate insulating film, a source region provided in the semiconductor region on one side of the gate electrode, and a drain region provided in the semiconductor region on the other side of the gate electrode. The source region is a region of either the first conductivity type or a second conductivity type having a higher impurity concentration than the semiconductor region of the first conductivity type. The drain region includes a Schottky barrier junction.

## Claims

### Claim 1

A tunnel FET comprising:
a semiconductor region of a first conductivity type;
a gate electrode provided on a surface portion of the semiconductor region via a gate insulating film;
a source region provided in the semiconductor region on one side of the gate electrode, the source region being a region of the first Conductivity type having a higher impurity concentration than the semiconductor region; and
a drain region provided in the semiconductor region on the other side of the gate electrode, the drain region comprising a metal silicide, wherein
an impurity concentration of a portion under the metal silicide is substantially the same as an impurity concentration of a channel under the gate electrode.

### Claim 2 (depends on 1)

The tunnel FET of claim 1, wherein the impurity concentration of the portion under the metal silicide of the drain region is set within a range of 5×1018 cm−3 to 2×1019 cm−3.

### Claim 3 (depends on 1)

The tunnel FET of claim 1, wherein a Fermi level of the metal silicide is between a conduction band (Ec) and a valence band (Ev) of silicon.

### Claim 4 (depends on 1)

The tunnel FET of claim 1, further comprising a metal silicide, which makes ohmic contact to the source region, provided in the source region.

### Claim 5 (depends on 1)

The tunnel FET of claim 1, wherein a voltage of the same polarity is applied to the gate electrode and the drain region.