# US 9,437,734 B2 · Semiconductor device with protective films and manufacturing method thereof

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- Number: US 9,437,734 B2
- Document ID: US9437734B2
- Status: Granted
- Kind: B2
- Application number: 13/196,984
- Filed: 2011-08-03
- Published: 2012-02-16
- Granted: 2016-09-06
- Earliest claimed: 2010-08-11
- Assignees: Lapis Semiconductor Co., Ltd.
- Applicants: Kiyotaka Yonekawa
- Inventors: Kiyotaka Yonekawa
- Web page: https://patentgrep.com/patent/US9437734B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 64/111: {Field plates}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6686: {the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane}
- H10P 14/6923: {the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate having a drain region, a source region and an impurity diffusion region; an oxide film formed on the impurity diffusion region; a first protective film including a SiN film as a principal component and being formed on the oxide film; and a second protective film containing carbon and being formed on the first protective film. A method of manufacturing the semiconductor device, includes doping an impurity into a semiconductor substrate, thereby forming a drain region, a source region and an impurity diffusion region; forming an oxide film on the impurity diffusion region; forming a first protective film including a SiN film as a principal component on the oxide film; and forming a second protective film containing carbon on the first protective film.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate including a drain part and a source part, the drain part and the source part being formed by doping an impurity into the semiconductor substrate;
a first dielectric layer formed in an area between the source part and the drain part, the first dielectric layer including a first portion and a second portion whose thickness is smaller than a thickness of the first portion;
a gate electrode formed on the area and disposed on the semiconductor substrate and the first and second portions of the first dielectric layer;
a second dielectric layer formed to cover the gate electrode and a surface of the semiconductor substrate;
a metal layer formed on the second dielectric layer;
a first pad being electrically connected to the source part;
a second pad being electrically connected to the drain part;
a first protective film including silicon nitride as a principal component and being formed on the second dielectric layer and formed to directly cover the metal layer; and
a second protective film containing carbon and being formed to directly cover the first protective film,
wherein the second protective film is formed by a CVD process using O3-TEOS.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein:
the first dielectric layer is formed between at least a part of the gate electrode and the semiconductor substrate;
the first portion and the second portion are arranged in a direction from the source part toward the drain part in this order; and
the thickness of the first portion is greater than the thickness of the second portion in a direction perpendicular to the semiconductor substrate.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising a first impurity diffusion layer, wherein the drain part is covered by the first impurity diffusion layer which has a lower impurity concentration than the drain part in the semiconductor substrate, the first impurity diffusion layer being formed so as to extend below the gate electrode.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, further comprising:
a first region and a second region in the semiconductor substrate, the second region being adjacent to the first region;
wherein the drain part, the source part and the impurity diffusion layer are formed in the first region; and
a drive control circuit for applying voltage to the drain part and the source part is formed in the second region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the first protective film traps electrons on a surface of the first protective film, when voltage is applied between the first pad and the second pad, and a current flows on the surface of the first protective film.

### Claim 6

A semiconductor device comprising:
a semiconductor substrate including a drain part and a source part, the drain part and the source part being formed by doping an impurity into the semiconductor substrate;
a first dielectric layer formed in an area between the source part and the drain part, the first dielectric layer including a first portion and a second portion whose thickness is smaller than a thickness of the first portion;
a gate electrode formed on the area and disposed on the semiconductor substrate and the first and second portions of the first dielectric layer;
a second dielectric layer formed to cover the gate electrode and a surface of the semiconductor substrate;
a metal layer formed on the second dielectric layer;
a first pad being electrically connected to the source part;
a second pad being electrically connected to the drain part;
a first protective film including silicon nitride as a principal component and being formed on the second dielectric layer and formed to directly cover the metal layer; and
a second protective film containing carbon and being formed to directly cover the first protective film,
wherein the second protective film is any of a phospho-silicate glass (PSG) film containing carbon, a boron phospho-silicate Glass (BPSG) film containing carbon, and an undoped silicon glass (USG) film containing carbon.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein
the first dielectric layer is formed between at least a part of the gate electrode and the semiconductor substrate,
the first portion and the second portion are arranged in a direction from the source part toward the drain part in this order, and
the thickness of the first portion is greater than the thickness of the second portion in a direction perpendicular to the semiconductor substrate.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6, further comprising a first impurity diffusion layer, wherein the drain part is covered by the first impurity diffusion layer which has a lower impurity concentration than the drain part in the semiconductor substrate, the first impurity diffusion layer being formed so as to extend below the gate electrode.

### Claim 9 (depends on 6)

The semiconductor device according to claim 6, wherein the first protective film traps electrons on a surface of the first protective film, when voltage is applied between the first pad and the second pad, and a current flows on the surface of the first protective film.