# US 9,437,733 B2 · Dynamic threshold MOS and methods of forming the same

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- Number: US 9,437,733 B2
- Document ID: US9437733B2
- Status: Granted
- Kind: B2
- Application number: 14/863,909
- Filed: 2015-09-24
- Published: 2016-01-14
- Granted: 2016-09-06
- Earliest claimed: 2013-10-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jam-Wem Lee
- Web page: https://patentgrep.com/patent/US9437733B2

## CPC

- H10D 30/0278: {forming single crystalline channels on wafers after forming insulating device isolations}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/6711: {by using electrodes contacting the supplementary regions or layers}
- H10D 30/721: {having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET (TFTs having gate-to-body connection H10D30/6708)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10P 10/128: {by direct semiconductor to semiconductor bonding}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.

## Claims

### Claim 1

A method comprising:
implanting a semiconductor substrate to form a well region extending from a back surface of the semiconductor substrate into the semiconductor substrate;
forming a well pickup region extending from the back surface of the semiconductor substrate into the well region;
forming a transistor at a front surface of the well region, wherein the forming the transistor comprises forming a gate electrode; and
forming metallic features electrically interconnecting the gate electrode and the well pickup region.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
forming first isolation regions extending from the back surface of the semiconductor substrate into the semiconductor substrate; and
forming second isolation regions extending from the front surface of the semiconductor substrate to the first isolation regions.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
before the forming the transistor, cleaving and planarizing the semiconductor substrate to expose the front surface of the well region.

### Claim 4 (depends on 3)

The method of claim 3 further comprising implanting hydrogen ions from a backside of the semiconductor substrate to form a hydrogen-concentrated layer in the semiconductor substrate, wherein the cleaving is performed along the hydrogen-concentrated layer to separate the semiconductor substrate into a first portion and a second portion, wherein the well region is located in the first portion.

### Claim 5 (depends on 1)

The method of claim 1 further comprising, after the forming the transistor:
forming a first interconnect structure on a front side of the semiconductor substrate;
bonding a wafer to the first interconnect structure; and
forming a second interconnect structure on a backside of the semiconductor substrate.

### Claim 6 (depends on 5)

The method of claim 5 further comprising forming a through-via penetrating through the semiconductor substrate, wherein the through-via is a part of the metallic features that is electrically coupled to the gate electrode.

### Claim 7 (depends on 1)

The method of claim 1, wherein the well region and the well pickup region have a same conductivity type, and an impurity concentration of the well pickup region is higher than an impurity concentration of the well region.

### Claim 8

A method comprising:
forming first isolation regions extending from a back surface of a semiconductor substrate into the semiconductor substrate;
cleaving a front portion of the semiconductor substrate to separate the front portion apart from a remaining portion of the semiconductor substrate, wherein a front surface of the front portion of the semiconductor substrate is exposed;
forming second isolation regions extending from the front surface of the semiconductor substrate to the first isolation regions; and
forming a transistor at the front surface of the semiconductor substrate.

### Claim 9 (depends on 8)

The method of claim 8, wherein the cleaving comprising:
implanting the semiconductor substrate to form a hydrogen-concentrated layer; and
annealing the semiconductor substrate and simultaneously applying a sideway mechanical force on the semiconductor substrate, wherein portions of the semiconductor substrate on opposite sides of the hydrogen-concentrated layer are separated from each other.

### Claim 10 (depends on 8)

The method of claim 8 further comprising forming metallic features electrically interconnecting a gate electrode of the transistor and a well pickup region of a well region in the semiconductor substrate.

### Claim 11 (depends on 8)

The method of claim 8 further comprising forming a well region extending from the back surface of the semiconductor substrate into the semiconductor substrate, wherein after the cleaving, the well region is exposed.

### Claim 12 (depends on 11)

The method of claim 11 further comprising forming a well pickup region extending from the back surface of the semiconductor substrate into the well region.

### Claim 13 (depends on 8)

The method of claim 8 further comprising forming a through-via penetrating through the semiconductor substrate.

### Claim 14 (depends on 13)

The method of claim 13, wherein the through-via further penetrates through one of the first isolation regions and one of the second isolation regions.

### Claim 15

A method comprising:
forming first isolation regions extending from a back surface of a semiconductor substrate into the semiconductor substrate;
forming a well region extending from the back surface of the semiconductor substrate into the semiconductor substrate;
forming a well pickup region extending from the back surface of the semiconductor substrate into the well region;
implanting the semiconductor substrate to form a hydrogen-concentrated layer, wherein the hydrogen-concentrated layer is spaced apart from the first isolation regions;
annealing the semiconductor substrate and simultaneously applying a sideway mechanical force on the semiconductor substrate to remove a portion of the semiconductor substrate, with a front surface of the semiconductor substrate exposed; and
forming second isolation regions extending from the front surface of the semiconductor substrate to the first isolation regions.

### Claim 16 (depends on 15)

The method of claim 15 further comprising forming a transistor at a front surface of the well region, wherein the front surface of the well region is a part of the front surface of the semiconductor substrate.

### Claim 17 (depends on 16)

The method of claim 16, wherein the front surface of the semiconductor substrate is spaced apart from the first isolation regions by a layer of the semiconductor substrate, and the forming the transistor further comprises forming a source/drain region in the layer of the semiconductor substrate.

### Claim 18 (depends on 15)

The method of claim 15 further comprising, after the annealing, planarizing the front surface of the semiconductor substrate.

### Claim 19 (depends on 15)

The method of claim 15 further comprising forming a through-via penetrating through the semiconductor substrate.

### Claim 20 (depends on 19)

The method of claim 19, wherein the through-via further penetrates through one of the first isolation regions.