# US 9,437,732 B2 · Semiconductor device

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- Number: US 9,437,732 B2
- Document ID: US9437732B2
- Status: Granted
- Kind: B2
- Application number: 14/964,701
- Filed: 2015-12-10
- Published: 2016-04-07
- Granted: 2016-09-06
- Earliest claimed: 2012-05-18
- Assignees: Unisantis Electronics Singapore Pte. Ltd.
- Applicants: Unisantis Electronics Singapore Pte. Ltd.
- Inventors: Fujio Masuoka; Hiroki Nakamura
- Web page: https://patentgrep.com/patent/US9437732B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 64/664: {the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10W 20/43: Layouts of interconnections
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the bottom of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the top of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode.

## Claims

### Claim 1

A semiconductor device comprising:
a fin-shaped semiconductor layer on a semiconductor substrate and extending in a first direction;
a first insulating film around the fin-shaped semiconductor layer;
a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer, a width of a bottom of the pillar-shaped semiconductor layer, perpendicular to the first direction, being equal to a width of a top of the fin-shaped semiconductor layer perpendicular to the first direction;
a gate insulating film around the pillar-shaped semiconductor layer;
a metal gate electrode around the gate insulating film; and
a metal gate line extending in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and connected to the metal gate electrode.