# US 9,437,730 B2 · Semiconductor device using three dimensional channel

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- Number: US 9,437,730 B2
- Document ID: US9437730B2
- Status: Granted
- Kind: B2
- Application number: 14/803,265
- Filed: 2015-07-20
- Published: 2016-05-26
- Granted: 2016-09-06
- Earliest claimed: 2014-11-21
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Kwan-Young Kim; Jae-Hyun Yoo; Jin-Hyun Noh; Woo-Yeol Maeng; Yong-Woo Jeon
- Inventors: Kwan-Young Kim; Jae-Hyun Yoo; Jin-Hyun Noh; Woo-Yeol Maeng; Yong-Woo Jeon
- Web page: https://patentgrep.com/patent/US9437730B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/154: {Dispositions}
- H10D 62/156: {Drain regions of DMOS transistors}
- H10D 62/158: {Dispositions}
- H10D 64/511: {for IGFETs}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10W 20/43: Layouts of interconnections
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.

## Claims

### Claim 1

A semiconductor device comprising:
a first fin;
a second fin that is separated from the first fin; and
a gate on the first fin and the second fin,
the gate crossing the first fin and the second fin,
the first fin including a first doped area at both sides of the gate, the first doped area being configured to have a first voltage applied thereto, and
the second fin including a second doped area at both sides of the gate, the second doped area configured to have a second voltage applied thereto, the second voltage being different than the first voltage.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein
the first fin includes a first well of a first conductive type,
the first well is formed along a first direction under a lower part of the gate,
the gate extends lengthwise in the first direction.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein
the first fin extends lengthwise in a second direction,
the second direction is different than the first direction,
the first well extends along the second direction in the first fin, and
the first doped area is in the first well.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein
the second fin extends lengthwise in the second direction,
a second well of a second conductive type is formed in at least a part within the second fin,
the second conductive type is different than the first conductive type, and
the second doped area is in the second well.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a substrate, wherein
the first fin and the second fin are one of on the substrate and defined by the substrate,
a first well is in the first fin and a portion of the substrate under a lower part of the gate, and
a width of the first well under the lower part of the gate is greater than a width of the first fin.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first active area; and
a second active area separated from the first active area, wherein
the first fin is on the first active area, and
the second fin is on the second active area.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising:
a deep trench isolation layer (DTI) separating the first active area and the second active area from each other.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein
the first active area and the second active area are defined by a substrate,
the substrate includes a drift region between the first active area and the second active area and below a lower part of the gate, and
the semiconductor device is configured to flow an on current from the first doped area to the second doped area via the drift region if a turn-on voltage is applied to the gate.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the first fin is defined by a shallow trench isolation (STI) in the first active area.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein
the first active area defines a plurality of fins are formed therein,
the second active area defines a plurality of second fins formed therein, and
the gate crosses the plurality of first fins and the plurality of second fins.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first wire connected to the first doped area, the first wire extending parallel to the first fin; and
a second wire connected to the second doped area, the second wire extending parallel to the second fin.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first wire and the second wire are in an M1 wire level.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, further comprising:
a dummy gate, wherein
the first fin includes a first long side and a first short side,
the second fin includes a second long side and a second short side, and the first long side faces the second long side, and
the dummy gate is on the first short side and the second short side.

### Claim 14 (depends on 1)

The semiconductor of claim 1, wherein the semiconductor device is a laterally diffused MOS (LDMOS) or a drain extended MOS (DEMOS).

### Claim 15 (depends on 1)

The semiconductor device of claim 1, further comprising:
an insulating layer between the first fin and the second fin, wherein
the gate crosses the first fin, the second fin, and the insulating layer,
the first fin includes a first well of a first conductive type,
the first well is formed in the first fin and in the second fin,
the first well extends below a lower part of the insulating layer that overlaps with the gate,
a part of the second fin includes a second well of a second conductive type that is different than the first conductive type,
the first fin includes a drain formed in the first well, and
the second fin includes a source formed in the second well.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, comprising:
a layer, wherein
the layer defines the first fin and the second fin,
the first and second fins are spaced apart from each other in a first direction and extend in a second direction that crosses the first direction,
the first fin includes a plurality of first doped areas of a first conductive type that are spaced apart from each other,
the second fin includes a plurality of second doped areas that are spaced apart from each other,
the gate is on the layer,
the gate extends in the first direction over the first fin between the first doped areas and over the second fin between the second doped areas, and
the gate extends over a portion of the layer between the first and second fins.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising:
a gate insulating layer between the gate and the layer, wherein
the layer includes a first well of the first conductive type and a second well of the second conductive type,
the second well extend in the second fin such that the second doped areas are formed in the second well, and
the first well extends into the first fin, the portion of the layer, and into a portion of the second fin under the gate, such that the first doped areas of the first fin are formed in the first well and the first well extends between parts of the second well in the second fin.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, further comprising:
a first wire electrically connected to the first doped areas; and
a second wire electrically connected to the second doped areas, wherein
the first wire is configured to apply a first voltage to the first doped areas,
the second wire is configured to apply a second voltage to the second doped areas,
the first and second voltages are different, and
the semiconductor device is configured to flow an on current from one of the first doped areas to one of the second doped areas via the portion of the layer if a turn-on voltage is applied to the gate.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the layer is one of
a semiconductor substrate, and
an epitaxial layer.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein
the layer includes a first active area and a second active area defined by a deep trench formed in the layer, and
the first fin and the second fin are defined by a shallow trench formed in the first active area and the second active area.