# US 9,437,729 B2 · High-density power MOSFET with planarized metalization

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- Number: US 9,437,729 B2
- Document ID: US9437729B2
- Status: Granted
- Kind: B2
- Application number: 11/651,258
- Filed: 2007-01-08
- Published: 2008-07-10
- Granted: 2016-09-06
- Earliest claimed: 2007-01-08
- Assignees: Vishay-Siliconix
- Applicants: Jian Li
- Inventors: Jian Li
- Web page: https://patentgrep.com/patent/US9437729B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 52/402: {of semiconductor materials}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for producing a power MOSFET. The method includes fabricating a plurality of layers of a power MOSFET to produce an upper surface active area and performing a chemical mechanical polishing process on the active area to produce a substantially planar surface. A metalization deposition process is then performed on the substantially planar surface and the fabrication of the power MOSFET is subsequently completed.

## Claims

### Claim 1

A method for producing a power MOSFET, comprising:
fabricating a plurality of layers of a power MOSFET and an integrated Schottky device to produce an upper surface active area;
performing a chemical mechanical polishing process on the upper surface active area to produce a substantially planar surface, wherein a gate contact is coplanar with an oxide deposit, wherein the oxide deposit comprises a source region, and wherein the oxide deposit comprises a drain region;
performing a metalization deposition process on the substantially planar surface, wherein a portion of the metallization deposition is in contact with the gate contact; and
completing fabrication of the power MOSFET and Schottky device.

### Claim 2 (depends on 1)

The method of claim 1 wherein the active area comprises silicon dioxide sub-areas and tungsten sub-areas.

### Claim 3 (depends on 2)

The method of claim 2 wherein the chemical mechanical polishing process comprises a tungsten optimized process.

### Claim 4 (depends on 1)

The method of claim 1 wherein the metalization deposition is configured to deposit a metal layer less than 4 microns deep.

### Claim 5 (depends on 4)

The method of claim 4 wherein the metal layer is configured to accept a plurality of wire bonds for completing fabrication of the power MOSFET.

### Claim 6 (depends on 1)

The method of claim 1 wherein the power MOSFET is a high density power MOSFET.

### Claim 7

A method for producing a high density power MOSFET, comprising:
fabricating a plurality of layers of a power MOSFET and an integrated Schottky device to produce an upper surface active area;
performing a chemical mechanical polishing process on the upper surface active area to produce a substantially planar surface, wherein a gate contact is coplanar with an oxide deposit, wherein the oxide deposit comprises a source region, and wherein the oxide deposit comprises a drain region;
performing a metalization deposition process on the substantially planar surface, wherein the metalization deposition is configured to deposit a metal layer less than 4 microns deep, wherein a portion of the metallization deposition is in contact with the gate contact; and
completing fabrication of the power MOSFET and Schottky device.

### Claim 8 (depends on 7)

The method of claim 7 wherein the active area comprises silicon dioxide sub-areas and tungsten sub-areas.

### Claim 9 (depends on 8)

The method of claim 8 wherein the chemical mechanical polishing process comprises a tungsten optimized process.

### Claim 10 (depends on 7)

The method of claim 7 wherein the metalization deposition is configured to deposit a metal layer less than 2 microns deep.

### Claim 11 (depends on 10)

The method of claim 10 wherein the metal layer is configured to accept a plurality of wire bonds for completing fabrication of the power MOSFET.

### Claim 12 (depends on 7)

The method of claim 7 wherein the upper surface of the active area is a high aspect ratio surface.

### Claim 13 (depends on 7)

The method of claim 7 wherein the power MOSFET is an N channel device or a P channel device.

### Claim 14 (depends on 7)

The method of claim 7 wherein the integrated Schottky device comprises a region larger than a gate contact region of the power MOSFET.

### Claim 15 (depends on 10)

The method of claim 10 wherein the upper surface of the active area is a high aspect ratio surface, and wherein the power MOSFET is an N channel device or a P channel device, and wherein the integrated Schottky device comprises a region larger than a source contact region of the power MOSFET.