# US 9,437,727 B2 · Semiconductor element including active region, low resistance layer and vertical drift portion

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- Number: US 9,437,727 B2
- Document ID: US9437727B2
- Status: Granted
- Kind: B2
- Application number: 14/643,651
- Filed: 2015-03-10
- Published: 2015-07-02
- Granted: 2016-09-06
- Earliest claimed: 2013-01-16
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Yasuhiko Onishi
- Web page: https://patentgrep.com/patent/US9437727B2

## CPC

- H10D 30/665: {having edge termination structures}
- H10D 62/052: {by forming stacked epitaxial layers}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 64/111: {Field plates}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 34/40: with high-energy radiation
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A drain drift portion is a first parallel p-n structure, largely corresponding to a portion directly below a p-type base region forming an active region, formed by first n-type regions and first p-type regions being alternately and repeatedly joined. The periphery of the drain drift portion is an edge termination region formed of a second parallel p-n structure aligned contiguously to the first parallel p-n structure and formed by second n-type regions and second p-type regions being alternately and repeatedly joined. An n-type buffer layer is provided between the first and second parallel p-n structures and an n+ type drain layer. A p+ type drain region is selectively provided inside the n+ type drain layer in the edge termination region, penetrating the n+ type drain layer in the depth direction.

## Claims

### Claim 1

A semiconductor device having an active region, existing on a first main surface side of a substrate, that causes current to flow actively or passively, a first conductivity type low resistance layer that exists in a surface layer on a second main surface side of the substrate, and a vertical drift portion, interposed between the active region and the first conductivity type low resistance layer, through which a drift current flows in a vertical direction in an on-state and which depletes in an off-state, wherein the vertical drift portion forms a first parallel p-n structure formed by first vertical first conductivity type regions oriented in the thickness direction of the substrate and first vertical second conductivity type regions oriented in the thickness direction of the substrate being alternately and repeatedly joined,
the semiconductor device comprising:
an edge termination region, interposed between the first main surface side and first conductivity type low resistance layer on the periphery of the vertical drift portion, that is largely a non-current path region in an on-state and depletes in an off-state;
a first conductivity type layer, provided from the active region to the edge termination region between the first parallel p-n structure and first conductivity type low resistance layer, that has resistance higher than that of the first conductivity type low resistance layer;
a second conductivity type low resistance layer selectively provided in a surface layer on the second main surface side in the edge termination region; and
an electrode in contact with the first conductivity type low resistance layer and the second conductivity type low resistance layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type low resistance layer is higher than the impurity concentration of the first conductivity type layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type low resistance layer is higher than the impurity concentration of the first conductivity type low resistance layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
further comprising a plurality of second conductivity type base regions provided on the first main surface side, wherein
an inner end portion of the second conductivity type low resistance layer is positioned at the boundary of the active region and edge termination region, and
an outer end portion of the second conductivity type low resistance layer is positioned separated outward from an outer end portion of the second conductivity type base region of the plurality of second conductivity type base regions provided farthest to the exterior by the thickness of the vertical drift portion or more.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the second conductivity type low resistance layer is provided from the boundary of the active region and edge termination region to the periphery of the edge termination region.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the second conductivity type low resistance layer is provided in a surface layer on the second main surface side of the first conductivity type low resistance layer, and
the first conductivity type low resistance layer is interposed between the second conductivity type low resistance layer and the first conductivity type layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the edge termination region forms a second parallel p-n structure formed by second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate being alternately and repeatedly joined.

### Claim 8 (depends on 2)

The semiconductor device according to claim 2, wherein the edge termination region forms a second parallel p-n structure formed by second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate being alternately and repeatedly joined.

### Claim 9 (depends on 3)

The semiconductor device according to claim 3, wherein the edge termination region forms a second parallel p-n structure formed by second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate being alternately and repeatedly joined.

### Claim 10 (depends on 4)

The semiconductor device according to claim 4, wherein the edge termination region forms a second parallel p-n structure formed by second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate being alternately and repeatedly joined.

### Claim 11 (depends on 5)

The semiconductor device according to claim 5, wherein the edge termination region forms a second parallel p-n structure formed by second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate being alternately and repeatedly joined.

### Claim 12 (depends on 6)

The semiconductor device according to claim 6, wherein the edge termination region forms a second parallel p-n structure formed by second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate being alternately and repeatedly joined.