# US 9,437,724 B2 · Semiconductor device and method of manufacturing the semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,724 B2 - Document ID: US9437724B2 - Status: Granted - Kind: B2 - Application number: 14/680,050 - Filed: 2015-04-06 - Published: 2015-10-22 - Granted: 2016-09-06 - Earliest claimed: 2014-04-21 - Assignees: Panasonic Intellectual Property Management Co., Ltd. - Applicants: Panasonic Intellectual Property Management Co., Ltd. - Inventors: Hiroaki Ueno - Web page: https://patentgrep.com/patent/US9437724B2 ## CPC - H10D 30/472: {having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10D 84/0123: {Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs} - H10D 84/05: using Group III-V technology - H10D 84/82: of only field-effect components - H03K 2017/6875: {using self-conductive, depletion FETs} - H03K 2217/0036: Means reducing energy consumption - H10D 62/343: {Gate regions of field-effect devices having PN junction gates} - H10D 62/357: {of FETs} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates} - H10D 64/602: {Heterojunction gate electrodes for FETs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A semiconductor device comprises a substrate, a semiconductor multilayer structure supported by the substrate, and a first nitride transistor provided in a first area of the semiconductor multilayer structure. The semiconductor multilayer structure comprises first to fourth nitride semiconductor layers. The first nitride transistor comprises part of the first nitride semiconductor layer, part of the second nitride semiconductor layer, part of the third nitride semiconductor layer, part of the fourth nitride semiconductor layer, a first gate electrode electrically connected to the part of the first nitride semiconductor layer, a first source electrode electrically connected to one of two portions in the third nitride semiconductor layer, a first drain electrode electrically connected to the other one of the two portions, and a first substrate electrode electrically connected to the part of the fourth nitride semiconductor layer. ## Claims ### Claim 1 A semiconductor device comprising: a substrate; a semiconductor multilayer structure supported by the substrate; a first nitride transistor provided in a first area of the semiconductor multilayer structure; and a second nitride transistor provided in a second area different from the first area in the semiconductor multilayer structure, wherein: the semiconductor multilayer structure comprises: a first nitride semiconductor layer; a second nitride semiconductor layer; a third nitride semiconductor layer having a band gap narrower than a band gap of the second nitride semiconductor layer; a fourth nitride semiconductor layer having an electric resistance value larger than an electric resistance value of the third nitride semiconductor layer, and a semi-insulating nitride semiconductor layer located between the substrate and the first nitride semiconductor layer, the first nitride semiconductor layer is located between the substrate and the second nitride semiconductor layer, the third nitride semiconductor layer is located between the second nitride semiconductor layer and the fourth nitride semiconductor layer, the second nitride semiconductor layer and the third nitride semiconductor layer are located between the first nitride semiconductor layer and the fourth nitride semiconductor layer, the first nitride transistor comprises: part of the first nitride semiconductor layer, part of the second nitride semiconductor layer, part of the third nitride semiconductor layer, and part of the fourth nitride semiconductor layer, the parts of the first to fourth semiconductor layers being located in the first area of the semiconductor multilayer structure; a first gate electrode electrically connected to the part of the first nitride semiconductor layer; a first source electrode electrically connected to one of two portions in the third nitride semiconductor layer, and a first drain electrode electrically connected to the other one of the two portions in the third nitride semiconductor layer, the two portions being spaced by a predetermined distance; and a first substrate electrode electrically connected to the part of the fourth nitride semiconductor layer, the second nitride transistor comprising: part of the first nitride semiconductor layer, part of the second nitride semiconductor layer, part of the third nitride semiconductor layer, and part of the semi-insulating nitride semiconductor layer, the parts of the first to third nitride semiconductor layers being located in the second area of the semiconductor multilayer structure; a second substrate electrode electrically connected to the part of the semi-insulating nitride semiconductor layer; a second source electrode electrically connected to one of two portions in the first nitride semiconductor layer, and a second drain electrode electrically connected to the other one of the two portions in the first nitride semiconductor layer, the two portions being spaced by a predetermined distance; and a second gate electrode electrically connected to the part of the third nitride semiconductor layer, and the second nitride semiconductor layer has the band gap wider than a band gap of the first nitride semiconductor layer. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first nitride semiconductor layer has an electric resistance value smaller than an electric resistance value of the semi-insulating nitride semiconductor layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, further comprising an element isolation structure configured to isolate the first area from the second area in the semiconductor multilayer structure. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the first nitride semiconductor layer and the third nitride semiconductor layer have conductivity types opposite to each other. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein an interface between the first nitride semiconductor layer and the second nitride semiconductor layer, and an interface between the second nitride semiconductor layer and the third nitride semiconductor layer are each depleted, when no voltage is applied to the first and second gate electrodes in the first nitride transistor and the second nitride transistor.