# US 9,437,723 B2 · Manufacturing method of semiconductor device including indium

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- Number: US 9,437,723 B2
- Document ID: US9437723B2
- Status: Granted
- Kind: B2
- Application number: 14/445,135
- Filed: 2014-07-29
- Published: 2015-02-12
- Granted: 2016-09-06
- Earliest claimed: 2013-08-12
- Assignees: Fujitsu Limited
- Applicants: Fujitsu Limited
- Inventors: Masato Nishimori; Toshihide Kikkawa
- Web page: https://patentgrep.com/patent/US9437723B2

## CPC

- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 30/206: {into Group III-V semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 95/904: {of Group III-V semiconductors}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/602: {Heterojunction gate electrodes for FETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes an electron transit layer configured to be formed on a substrate; an electron supply layer configured to be formed on the electron transit layer; an upper surface layer configured to be formed on the electron supply layer; a gate electrode configured to be formed on the electron supply layer or the upper surface layer; a source electrode and a drain electrode configured to be formed on the upper surface layer; and first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed. The electron supply layer is formed of a nitride semiconductor including In. The upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.

## Claims

### Claim 1

A manufacturing method of the semiconductor device, the method further comprising:
forming an electron transit layer, an electron supply layer, and an upper surface layer in order on a substrate by epitaxial growth;
implanting ions of an impurity element of a first conductivity-type in regions immediately below where a source electrode and a drain electrode are to be formed in the electron supply layer and the upper surface layer;
forming a heat-protective film on the upper surface layer after the implanting the ions of the impurity element of the first conductivity-type; and
applying heat to activate the implanted ions so that the regions with the implanted ions become first conductivity-type regions;
removing the heat-protective film and all of the upper surface layer;
forming the source electrode and the drain electrode on one of the electron supply layer, and the electron transit layer; and
forming a gate electrode on the electron supply layer,
wherein the electron supply layer is formed of a nitride semiconductor including In,
wherein the upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.

### Claim 2 (depends on 1)

The manufacturing method of the semiconductor device as claimed in claim 1, wherein the impurity element of the first conductivity-type is Si, and the applying heat is performed at a temperature greater than or equal to 900° C. and less than or equal to 1500° C.