# US 9,437,722 B2 · High-voltage vertical power component

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- Number: US 9,437,722 B2
- Document ID: US9437722B2
- Status: Granted
- Kind: B2
- Application number: 14/510,663
- Filed: 2014-10-09
- Published: 2015-04-23
- Granted: 2016-09-06
- Earliest claimed: 2013-10-17
- Assignees: STMicroelectronics (Tours) SAS; Universite Francois Rabelais
- Applicants: STMicroelectronics (Tours) SAS; Universite Francois Rabelais
- Inventors: Samuel Menard; Gael Gautier
- Web page: https://patentgrep.com/patent/US9437722B2

## CPC

- H10D 18/021: {of bidirectional devices, e.g. triacs}
- H10D 8/80: PNPN diodes, e.g. Shockley diodes or break-over diodes
- H10D 18/80: Bidirectional devices, e.g. triacs
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/113: {Isolations within a component, i.e. internal isolations}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/53: the imperfections being within the semiconductor body
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well.

## Claims

### Claim 1

A vertical power component, comprising:
a silicon substrate doped with a first conductivity type and having an upper surface and a lower surface opposite said upper surface;
a first well in the lower surface of said silicon substrate doped with a second conductivity type;
a second well in the upper surface of said silicon substrate doped with the second conductivity type;
a first insulating porous silicon ring surrounding said first well and having a lower surface aligned with the lower surface of the silicon substrate, a depth which exceeds a thickness of the first well and an upper surface in contact with the first conductivity type silicon substrate, said first insulating porous silicon ring in contact with a junction between the first well and the silicon substrate; and
a second insulating porous silicon ring surrounding said second well and having an upper surface aligned with the upper surface of the silicon substrate, a depth which exceeds a thickness of the second well and a lower surface in contact with the first conductivity type silicon substrate, said second insulating porous silicon ring in contact with a junction between the second well and the silicon substrate; and
wherein the first and second porous silicon rings are not in contact with each other.

### Claim 2 (depends on 1)

The component of claim 1, further comprising:
a first electrode in contact with the first well on the lower surface of the silicon substrate; and
a second electrode in contact with the second well on the upper surface of the silicon substrate.

### Claim 3 (depends on 2)

The component of claim 2, further comprising: a gate electrode in contact with the second well on the upper surface of the silicon substrate, the gate electrode insulated from said second electrode.

### Claim 4 (depends on 3)

The component of claim 3, further comprising a heavily doped region of the first conductivity type in said second well which is in contact with said gate electrode.

### Claim 5 (depends on 2)

The component of claim 2, further comprising:
a first heavily doped region of the first conductivity type in said first well which is in contact with said first electrode; and
a second heavily doped region of the first conductivity type in said second well which is in contact with said second electrode.