# US 9,437,721 B2 · Reverse-conducting IGBT with buffer layer and separation layer for reducing snapback

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- Number: US 9,437,721 B2
- Document ID: US9437721B2
- Status: Granted
- Kind: B2
- Application number: 14/964,772
- Filed: 2015-12-10
- Published: 2016-03-31
- Granted: 2016-09-06
- Earliest claimed: 2013-11-26
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Tetsuo Takahashi
- Web page: https://patentgrep.com/patent/US9437721B2

## CPC

- H10D 84/617: {Combinations of vertical BJTs and only diodes}
- H10D 1/47: Resistors having no potential barriers
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/133: {Emitter regions of BJTs}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 84/403: {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In the reverse-conducting IGBT according to the present invention, an n-type buffer layer surrounds a p-type collector layer. A p-type separation layer surrounds an n-type cathode layer. The n-type buffer layer separates the p-type collector layer and the p-type separation layer from each other. The p-type separation layer separates the n-type cathode layer and the n-type buffer layer from each other. Therefore, the present invention makes it possible to reduce snapback.

## Claims

### Claim 1

A semiconductor device comprising:
an n-type drift layer;
a p-type base layer in a channel region on the n-type drift layer;
an n-type emitter layer on the p-type base layer;
a trench-gate electrode penetrating the p-type base layer and the n-type emitter layer and being in contact with the p-type base layer and the n-type emitter layer through a gate insulating film;
a p-type anode layer in a region other than the channel region on the n-type drift layer;
an emitter electrode connected to the n-type emitter layer and the p-type anode layer;
a p-type collector layer below the n-type drift layer;
an n-type cathode layer below the n-type drift layer;
a collector electrode connected to the p-type collector layer and the n-type cathode layer;
an n-type buffer layer provided between the n-type drift layer and the p-type collector layer;
a p-type separation layer provided between the n-type drift layer and the n-type cathode layer; and
an embedded oxide film separating the p-type collector layer and the p-type separation layer from each other and separating the n-type cathode layer and the n-type buffer layer from each other.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the p-type collector layer is larger than a width of the n-type cathode layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising an emitter connection resistor connected between the emitter electrode and the n-type emitter layer.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, further comprising a first contact hole connecting the n-type emitter layer to the emitter electrode, and a second contact hole connecting the p-type base layer to the emitter electrode,
wherein the first contact hole and the second contact hole are separated from each other.

### Claim 5 (depends on 3)

The semiconductor device according to claim 3, wherein surface concentration of the n-type emitter layer is lower than peak concentration of the n-type emitter layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein at least a part of the n-type cathode layer is arranged immediately below the p-type anode layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein one p-type anode layer is provided for the plurality of channel regions.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, further comprising a p-type well layer in a terminal region and connected to the emitter electrode,
wherein the n-type cathode layer is not provided immediately below the p-type well layer.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, further comprising a p-type well layer in a terminal region and connected to the emitter electrode, and an embedded oxide film provided between the n-type drift layer and the collector electrode immediately below the p-type well layer.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, further comprising an emitter connection resistor connected between the emitter electrode and the p-type well layer.