# US 9,437,718 B1 · Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having a wide band gap emitter/collector which are epitaxially grown

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- Number: US 9,437,718 B1
- Document ID: US9437718B1
- Status: Granted
- Kind: B1
- Application number: 14/709,579
- Filed: 2015-05-12
- Granted: 2016-09-06
- Earliest claimed: 2015-05-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Jin Cai; Kevin K. Chan; Tak H. Ning; Jeng-Bang Yau; Joonah Yoon
- Web page: https://patentgrep.com/patent/US9437718B1

## CPC

- H10D 10/80: Heterojunction BJTs
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/041: {of thin-film BJTs (of heterojunction BJTs H10D10/021)}
- H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)}
- H10D 10/311: {Thin-film BJTs}
- H10D 10/60: Lateral BJTs
- H10D 62/114: {PN junction isolations}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/134: {of lateral BJTs}
- H10D 62/136: {of heterojunction BJTs (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D10/861)}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/8325: {Silicon carbide}
- H10P 14/274: {using seed materials}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor structure includes forming a first seed layer, a second seed layer and an intrinsic base spaced apart from each other and with the intrinsic base located between the first seed layer and the second seed layer on an insulator layer. The method further includes forming an emitter on the first seed layer and on a first vertical surface of the intrinsic base by epitaxially growing the emitter from the first seed layer and the first vertical surface of the intrinsic base, and forming a collector on the second seed layer and on a second vertical surface of the intrinsic base by epitaxially growing the collector from the second seed layer and the second vertical surface of the intrinsic base.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
forming a first seed layer, a second seed layer and an intrinsic base spaced apart from each other, wherein the intrinsic base is located between the first seed layer and the second seed layer and on an insulator layer, wherein a first gap is located between the first seed layer and a first vertical surface of the intrinsic base, and a second gap is located between the second seed layer and a second vertical surface of the intrinsic base, wherein the first seed layer, the second seed layer and the intrinsic base include a semiconductor material and have a doping of a first conductivity type;
forming an emitter on the first seed layer, and in the first gap and on the first vertical surface of the intrinsic base by epitaxially growing the emitter from the first seed layer and the first vertical surface of the intrinsic base; and
forming a collector on the second seed layer, and in the second gap and on the second vertical surface of the intrinsic base by epitaxially growing the collector from the second seed layer and the second vertical surface of the intrinsic base, wherein the emitter and the collector have a doping of a second conductivity type opposite to the first conductivity type, and wherein a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the first seed layer, the second seed layer and the intrinsic base comprises:
providing a semiconductor portion on the insulator layer, said semiconductor portion is surrounded by a trench isolation structure;
forming an epitaxy portion including a semiconductor material on a top surface of the semiconductor portion by epitaxially growing the epitaxy portion on the top surface of the semiconductor portion; and
etching the semiconductor portion using the epitaxy portion as an etch mask to form the first seed layer, the second seed layer and the intrinsic base.

### Claim 3 (depends on 2)

The method of claim 2, wherein prior to forming the epitaxy portion, the method further comprises:
forming an extrinsic base on the top surface of the semiconductor portion, wherein the extrinsic base has a doping of the first conductivity type.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
forming an insulator cap on a top surface of the extrinsic base; and
forming an insulating spacer laterally surrounding and contacting the extrinsic base and the insulator cap.

### Claim 5 (depends on 4)

The method of claim 4, wherein the epitaxy portion is formed by epitaxially growing the epitaxy portion from the top surface of the semiconductor portion using a selective epitaxial growth (SEG) process, and wherein the epitaxy portion grown on the top surface of the semiconductor portion also contacts an edge of a top surface of the trench isolation structure and an edge of a lower portion of the insulating spacer prior to the etching of the semiconductor portion.

### Claim 6 (depends on 3)

The method of claim 3, wherein the first conductivity type is a p-type conductivity and the second conductivity type is an n-type conductivity, and wherein an energy band gap of the intrinsic base is less than an energy band gap of the emitter, an energy band gap of the collector, and further wherein a doping concentration of the intrinsic base is less than a doping concentration of the extrinsic base.

### Claim 7 (depends on 3)

The method of claim 3, wherein the first conductivity type is an n-type conductivity and the second conductivity type is a p-type conductivity, and wherein an energy band gap of the intrinsic base is less than an energy band gap of the emitter, an energy band gap of the collector, and further wherein a doping concentration of the intrinsic base is less than a doping concentration of the extrinsic base.

### Claim 8 (depends on 3)

The method of claim 3, wherein the emitter and the collector each include silicon, silicon germanium, or a combination thereof, wherein the intrinsic base, the first seed layer and the second seed layer each include germanium or silicon germanium, wherein the emitter and the collector each have an n-type conductivity, wherein the intrinsic base, the first seed layer, the second seed layer and the extrinsic base each have p-type conductivity, wherein an energy band gap of the intrinsic base, the first seed layer and the second seed layer is less than an energy band gap of the extrinsic base, and wherein a doping concentration of the intrinsic base, the first seed layer and the second seed layer is less than a doping concentration of the extrinsic base.

### Claim 9 (depends on 2)

The method of claim 2, wherein the providing the semiconductor portion on the insulator layer comprises:
providing a semiconductor-on-insulator substrate; and
patterning a top semiconductor layer of the semiconductor-on-insulator substrate, wherein said patterning includes forming a trench in the top semiconductor layer and filling the trench with a trench dielectric material.

### Claim 10 (depends on 2)

The method of claim 2, wherein the epitaxy portion comprises Si, Ge, SiGe, SiGeC, SiC, or a combination thereof.

### Claim 11 (depends on 2)

The method of claim 2, wherein a selective silicon epitaxial (SEG) process is performed on all exposed surfaces of the first seed layer and an exposed surface of the first vertical surface of the intrinsic base to grow the emitter, wherein the emitter covers and contacts the first seed layer, the first vertical surface of the intrinsic base, fills the first gap between the first seed layer and the first vertical surface of the intrinsic base, and covers and contacts a first sidewall of the trench isolation structure, and
wherein a selective silicon epitaxial (SEG) process is performed on all exposed surfaces of the second seed layer and an exposed surface of the second vertical surface of the intrinsic base to grow the collector, wherein the collector covers and contacts the second seed layer, the second vertical surface of the intrinsic base, fills the second gap between the second seed layer and the second vertical surface of the intrinsic base, and covers and contacts a second sidewall of the trench isolation structure.

### Claim 12 (depends on 2)

The method of claim 2, wherein the emitter is epitaxially grown using a selective silicon epitaxial (SEG) process to form the emitter as a thin layer that conformally covers and contacts the first vertical surface of the intrinsic base, conformally covers and contacts the first seed layer, partially fills in the first gap between the first seed layer and the first vertical surface of the intrinsic base, and covers and contacts a first sidewall of the trench isolation structure, and wherein the collector is epitaxially grown using a selective silicon epitaxial (SEG) process to form the collector as a thin layer that conformally covers and contacts the second vertical surface of the intrinsic base, conformally covers and contacts the second seed layer, partially fills in the second gap between the second seed layer and the second vertical surface of the intrinsic base, and covers and contacts a second sidewall of the trench isolation structure.

### Claim 13 (depends on 1)

The method of claim 1, wherein the first gap is formed to have a V-shape that is defined by a sidewall of the first seed layer, the first vertical surface of the intrinsic base, and a first portion of a top surface of the insulator layer, and wherein the second gap is formed to have a V-shape that is defined by a sidewall of the second seed layer, the second vertical surface of the intrinsic base, and a second portion of the top surface of the insulator layer.

### Claim 14

A method of forming a semiconductor structure comprising:
providing a semiconductor-on-insulator (SOI) substrate;
patterning a top semiconductor layer of the SOI substrate to form a top semiconductor portion on an insulator layer of the SOI substrate, said top semiconductor portion is surrounded by a trench isolation structure, wherein the top semiconductor portion comprises Si, Ge, SiGe, SiGeC, SiC, or a combination thereof, and has a doping of a first conductivity type;
sequentially forming a stack of an extrinsic base and an insulator cap on a top surface of the top semiconductor portion, wherein the extrinsic base has a doping of the first conductivity type;
forming a first insulating spacer laterally surrounding and contacting the extrinsic base and the insulator cap;
performing a selective epitaxial growth (SEG) process on the top semiconductor portion to form a first sacrificial epitaxy portion on a first region of the top semiconductor portion located on a first side of the extrinsic base, and a second sacrificial epitaxy portion on a second region of the top semiconductor portion located on a second side the extrinsic base located opposite to the first side of the extrinsic base, wherein the first and second sacrificial epitaxy portions comprise Si, Ge, SiGe, SiGeC, SiC, or a combination thereof;
performing an anisotrophic etching on the top semiconductor portion using the first and second sacrificial epitaxy portions as an etching mask to form a first seed layer, a second seed layer and an intrinsic base spaced apart from each other and with the intrinsic base located between the first seed layer and the second seed layer on the insulator layer, wherein the stack of the extrinsic base and the insulator cap is located on a top surface of the intrinsic base, wherein there is a first gap located between the first seed layer and a first vertical surface of the intrinsic base, and a second gap located between the second seed layer and a second vertical surface of the intrinsic base, wherein the first seed layer, the second seed layer and the intrinsic base include a semiconductor material and have a doping of the first conductivity type;
performing an SEG process on all exposed portions of the first seed layer and an exposed surface of the first vertical surface of the intrinsic base to form an emitter as a continuous layer that covers and contacts the first vertical surface of the intrinsic base, covers and contacts the first seed layer, fills in the first gap, and covers and contacts a first sidewall of the trench isolation structure, wherein the emitter comprises Si, Ge, SiGe, SiGeC, SiC, or a combination thereof and has a doping of a second conductivity type opposite to the first conductivity type;
performing an SEG process on all exposed portions of the second seed layer and an exposed surface of the second vertical surface of the intrinsic base to form a collector as a continuous layer that covers and contacts the second vertical surface of the intrinsic base, covers and contacts the second seed layer, fills in the second gap, and covers and contacts a second sidewall of the trench isolation structure, wherein the collector comprises Si, Ge, SiGe, SiGeC, SiC, or a combination thereof and has a doping of the second conductivity type, and wherein the intrinsic base has an energy band gap less than an energy band gap of the emitter and an energy band gap of the collector;
forming a second insulating spacer laterally surrounding and contacting the first insulating spacer and contacting the emitter and the collector; and
removing the insulator cap on the extrinsic base by an anisotropic etching process.