# US 9,437,717 B2 · Interface control in a bipolar junction transistor

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- Number: US 9,437,717 B2
- Document ID: US9437717B2
- Status: Granted
- Kind: B2
- Application number: 13/971,982
- Filed: 2013-08-21
- Published: 2013-12-19
- Granted: 2016-09-06
- Earliest claimed: 2011-11-16
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Kevin K. Chan; Peng Cheng; Qizhi Liu; Ljubo Radic
- Web page: https://patentgrep.com/patent/US9437717B2

## CPC

- H10D 10/00: Bipolar junction transistors [BJT]
- G06F 30/30: Circuit design
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.

## Claims

### Claim 1

A bipolar junction transistor comprising:
an intrinsic base layer including a raised region with a first portion and a second portion, the second portion of the raised region being thinner than the first portion of the raised region, the intrinsic base layer including a top surface, a bulk layer, and an interface layer between the bulk layer and the top surface, the interface layer comprised of silicon, the bulk layer comprised of silicon-germanium, the interface layer of the first portion of the raised region has a first thickness, and the interface layer of the second portion of the raised region has a second thickness that is less than the first thickness;
an emitter in a contacting relationship with the interface layer of the first portion of the raised region of the intrinsic base layer at the top surface; and
an extrinsic base layer in a contacting relationship with the interface layer of the second portion of the raised region of the intrinsic base layer at the top surface,
wherein the emitter and the first portion of the raised region of the raised region of the intrinsic base layer are vertically arranged, and a p-n junction is located at an interface between the interface layer of the intrinsic base layer and the emitter.

### Claim 2 (depends on 1)

The bipolar junction transistor of claim 1 wherein the interface layer has a first thickness over the first portion of the raised region of the intrinsic base layer, the interface layer has a second thickness over the second portion of the raised region of the intrinsic base layer, and the second thickness is smaller than the first thickness.

### Claim 3 (depends on 1)

The bipolar junction transistor of claim 1 wherein further comprising:
a plurality of shallow trench isolation regions defining a device region, the device region aligned with the raised region of the intrinsic base layer; and
a collector in the device region, the collector comprised of a first semiconductor material having an opposite conductivity type from the intrinsic base layer.

### Claim 4 (depends on 3)

The bipolar junction transistor of claim 3 wherein the first portion of the raised region of the intrinsic base layer is disposed between the collector and the emitter.

### Claim 5 (depends on 1)

The bipolar junction transistor of claim 1 further comprising:
a plurality of non-conductive spacers on the emitter,
wherein the extrinsic base layer is self-aligned with the non-conductive spacers.

### Claim 6

A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a bipolar junction transistor, the HDL design structure comprising:
an intrinsic base layer including a raised region with a first portion and a second portion, the second portion of the raised region being thinner than the first portion of the raised region, the intrinsic base layer including a top surface, a bulk layer, and an interface layer between the bulk layer and the top surface, the interface layer comprised of silicon, and the bulk layer comprised of silicon-germanium, the interface layer of the first portion of the raised region has a first thickness, and the interface layer of the second portion of the raised region has a second thickness that is less than the first thickness;
an emitter in a contacting relationship with the interface layer of the first portion of the raised region of the intrinsic base layer at the top surface; and
an extrinsic base layer in a contacting relationship with the interface layer of the second portion of the raised region of the intrinsic base layer at the top surface,
wherein the emitter and the first portion of the raised region of the raised region of the intrinsic base layer are vertically arranged, and a p-n junction is located at an interface between the interface layer of the intrinsic base layer and the emitter.

### Claim 7 (depends on 6)

The HDL design structure of claim 6 wherein the HDL design structure comprises a netlist.

### Claim 8 (depends on 6)

The HDL design structure of claim 6 wherein the HDL design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

### Claim 9 (depends on 6)

The HDL design structure of claim 6 wherein the HDL design structure resides in a programmable gate array.

### Claim 10 (depends on 1)

The bipolar junction transistor of claim 1 further comprising:
a collector vertically arranged with the first portion of the raised region of the intrinsic base layer and the emitter, the collector in a contacting relationship with the bulk layer of the intrinsic base layer, and the collector separated from the emitter by the interface layer and bulk layer of the intrinsic base layer.